Don't break iommu_attach_device.
iommu_attach_device will break if iommu shared by two or more masters
Change-Id: Ifd1c652341e2270bfde57ebe1e0cd00d51d38eec
Signed-off-by: Simon Xue <xxm@rock-chips.com>
The deserializers convert a singleor dual-link GMSL2
serial input to embedded DisplayPort (eDP), enabling
display of high-resolution RGB888 video.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ief4d5a8ca9ed42c5954c8fc1403da58bebee4730
The MAX96776/MAX96778 deserializers convert singleor
dual-link GMSL™ serial input to embedded DisplayPort
(eDP) v1.4a. 600MHz PCLK capability and decompression
of VESA 3:1 DSC v1.1 enable transport of 4K (UHD),
24-bit, 60fps video over a single coax or twisted pair
link. The MAX96776/MAX96778 also send and receive
sidechannel and peripheral control data to enable
full-duplex single-wire transmission of video and
bidirectional data.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I3c07fc1053ae6080cb1cca1bfb9bca5fb38bb563
T3-p1 with 650mV output voltage is the best signal via the test.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5c2bd3ab0c235f3079925a03a59c419ad37da485
This series in order to have the default MMC alias.
The mmc default alias:
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio0;
The Linux OS have the post-build.sh to handle the rootfs,
and export RK_EXTRA_PARTITIONS for setting the PARTITIONS.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I27b5645200a645bee6c3dc2f4e95cdb23ba19ab8
Set both the DMA mask and the coherent DMA mask before drm master to
binder the components.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ia7ba80e4fddaf957e775e10348bacbf0568102bd
add rkispp-subdev pad2:Source set format API to support fec
crop output size by mesh size.
Change-Id: I8857547d1dc07ff033a50b1dc7bc2079a9221b12
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Fix the following fall-through warning:
drivers/pinctrl/pinctrl-max96755f.c:123:6: warning: this statement may fall through [-Wimplicit-fallthrough=]
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ib79fd9c76e4213709008a7d3102b9e2e033bf7d7
only enable 8K@12fps & 4K@30fps setting for use, others for debug
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I21faf9d961d7f90eed2d64e8da0f3bb4a980895e
1. 4224x3136@15fps & 2114x1568@60fps only enable for debug
2. fix some regs setting
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Iab37357aea55a66c51ef70a76383b8b7b26ffd14
For RK3588, the reset value of background is 0xa0080200, which
will enable background and output a grey image. But the reset
value is just valid in first frame and disable in follow frames.
If the panel backlight is valid before follow frames. The screen
may flick a grey image. To avoid this phenomenon appear, setting
black background after reset vop.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Iadf805a26d84c1dc49cb64a637588c43ecd32977
Fixes: de30a9e538 ("drm/rockchip: dw-dp: Support dp show uboot logo")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ib0e95ad4eaa88c7fd84f393d8c2dcceb4962a1b9
Enable the maxim serdes driver used on RK3588 vehicle.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I0ed611d2a14438e1fab76f97c2093804f4575940
On most of rockchip platforms, the usb2 phy lost power
during deep sleep. So we need to reset phy during pm
resume to recovery clock to usb controller.
When do sleeptest on rk3588 evb1, without this patch,
it may fail in ehci_resume or ohci_resume, because
the ehci/ohci controller can't get clock from usb2 phy.
Note that the phy reset is optional in devicetree, so
it needs to check the reset_control of phy before phy
reset operation to avoid unnecessary delay.
Fixes: ba8a6e65a7 ("phy: rockchip: inno_usb2: only reset phy if deassert iddq for rk3588")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I31dee9baea472d9e314eca6cb9f78b2aab0e5353
