The RGB interface also supports formats that have multiple cycles per
pixel, such as MEDIA_BUS_FMT_RGB888_3X8, MEDIA_BUS_FMT_RGB565_2X8_LE,
and so on. And the &drm_display_mode.crtc_clock should be multiplied by
the return value of rockchip_drm_get_cycles_per_pixel().
Fixes: 3cb261be89 ("drm/rockchip: drv: fix the dclk calculation of mcu interface")
Change-Id: Idbb6f6ef2ac17dc0dd63d67519733dbd1e29e9dd
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The RGB interface also supports formats that have multiple cycles per
pixel, such as MEDIA_BUS_FMT_RGB888_3X8, MEDIA_BUS_FMT_RGB565_2X8_LE,
and so on. And the &drm_display_mode.crtc_clock should be multiplied by
the return value of rockchip_drm_get_cycles_per_pixel().
Fixes: 3cb261be89 ("drm/rockchip: drv: fix the dclk calculation of mcu interface")
Change-Id: I85c0168ccfaedbf5566a2c6b8f86e881fbc93ad0
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
VOP sharp/post-scaler/split use the same line buffer.
They must be mutually exclusive, otherwise the picture
will display abnormally.
Change-Id: Ia8e7877826bf2a4484a4060ea4d704a2edc611c3
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Issue:
1. On arm32 platform iommu use the mapping->domain, while use the
group->domain on arm64 platform.
2. __iommu_attach_group use group->default to judge whether new device
in kernel 5.10 branch, while use group->domain in kernel 6.1 branch.
For this change, when two devices share the iommu, the first device
attach success, while the second device failed in kernel 6.1 branch.
Method:
1. Set driver_managed_dma=true to ensure that during the IOMMU probe
phase,
even if attach group failed, the mapping will not be released.
2. After the IOMMU probe succeeds, record info->domain=mapping->domain
and
detach it, ensuring that group->domain is set to NULL. This prevents
the
next device which sharing the IOMMU, not return -EBUSY when attach
the
group.
3. Before hardware running, the shared IOMMU should check whether the
device has been switched. If so, it needs to attach the current
device's info->domain.
4. When removing a shared IOMMU, it must also ensure that group->domain
corresponds to the current device.
Change-Id: If0fec01a0bcf9c49850129bfa5ac28484fece9a2
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
fix the crash caused by interrupt occurring before info->last_chan is ready
Change-Id: I6a57d49d5af6fb35708e009c33422ad936af0d3f
Signed-off-by: Simon Xue <xxm@rock-chips.com>
fix the variable naming conflict with "lock" when CONFIG_ROCKCHIP_SARADC_TEST_CHN enabled
Change-Id: I9f2925fb6e4be642cacf8e5d5c764e33d13b9cc4
Signed-off-by: Simon Xue <xxm@rock-chips.com>
According to the eDP v1.3 chapter 3.6 Table 3-15, Alternative
Scramble Seed Reset(ASSR) is a recommended way for eDP Sink devices
to support Display Authentication and Content Protection as Method
3a, while Method 1 HDCP is normally not expected in an eDP Sink
device.
In addition, the ASSR support capability should be the bit 0 of
DPCD register 0000Dh according to the eDP v1.4 'Revision History'
table 2:
......
Table 3-4: Corrected reference to DPCD Address 0000Dh, bit 0 (was bit 4)
......
Change-Id: Iafad97755fd4c9e688c47164d099b290af905036
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
For some connector drivers, such as dw-dp, &drm_bridge_funcs.atomic_check()
helps to select output_mode, color_range and so on, which will be
determined in the following &drm_encoder_helper_funcs.atomic_check().
In order to get the exact display mode for the mode comparison
between U-boot and Kernel, add the full bridge atomic check process
in rockchip_drm_mode_fixup().
Without this patch, the mode comparison will fail if the DP logo
display is enabled in YUV420 mode for RK3576, because the display
mode of uboot has been fixed while the display mode of kernel has
not, due to the incorrect conn_state->output_mode.
The related workaround is:
/*
* For RK3576 YUV420 output, hden signal introduce one cycle delay,
* so we need to adjust hfp and hbp to compatible with this design.
*/
if (vop2->version == VOP_VERSION_RK3576 &&
conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) {
mode->crtc_hsync_start += 2;
mode->crtc_hsync_end += 2;
}
Fixes: c4642391b1 ("drm/rockchip: vop2: adjust hfp and hbp for YUV420 output")
Change-Id: I3193bfa2bca7c14f5c7308f94e7d23160618be0c
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
