Add support hp-ctl gpio for amic board, and rename
to spk-ctl from dtsi file. Usually, we should assign
these output ctl gpios according to the specific
product type.
Change-Id: Icf0c29f61bed3c0f48069b9e38ddf47d921fed26
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We need to configure each ADC in parallel as much as
possible. The infos from vendor, we add some new
registers to make effect better:
1/ optimize the flows for enable/disable ADC/DAC flows
2/ add support fade-out digital gains for de-pop
3/ many updates
Change-Id: I2e72451201010de96e7dc5c22ff3384ce71767ea
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
When PMIC irq occurs, regmap-irq.c will traverse all PMIC child
interrupts from low index 0 to high index, we give fall interrupt
high priority to be called earlier than rise, so that it can be
override by late rise event. This can helps to solve key release
glitch which make a wrongly fall event immediately after rise.
Change-Id: Ieda1d6fd3c50cc36742a4740504ec7ce12ea509b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Setting inno phy config table in dts. According to tmds clock range, phy
config data can be chosen. We can also filter some video modes which
tmds clock out of range we set.
Change-Id: I666c825921877fe2cdf45c2ccd1415815a4b7715
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
For hotplug device the crtc->primary->fb should be equal to
fb_helper->fb, otherwise the following path will return false
and lead to connect state error:
->hotplug
->output_poll_changed()
->drm_fb_helper_hotplug_event()
->drm_fb_helper_is_bound()
after user space beging, the above path can return false, because
sometimes user space wants everything disabled, don't steal the display
if there's a master, so we set crtc->primary->fb point to the original
fb when drm_open.
Change-Id: I5343978ce602324dbdc3125b6b98a7b4233149ab
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The reason to implement shutdown is for the fake shutdown on the box
product. but after implement this function, panel will still display
overlay plane for about two second when power off. so we directly
close crtc instead of rockchip_drm_sys_suspend() when shutdown.
Change-Id: I60ed3e541e022ad828fd535828fe264aabd40ecb
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
When a usb device disconnects in a certain way, dwc2_queue_transaction
still gets called after dwc2_hcd_cleanup_channels.
dwc2_hcd_cleanup_channels does "channel->qh = NULL;" but
dwc2_queue_transaction still wants to dereference qh.
This adds a check for a null qh.
(am from https://patchwork.kernel.org/patch/7245251/)
Change-Id: Ia9c7f5febe0bb6f0123cfc85c90beb9fc1d80bdd
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
some low solutation SPI panel, the display content should be
send through the SPI interface, so add to get the kernel virtual
address, which can be accessed by cpu and SPI interface.
Change-Id: I9823162e682819309bf61d3b132eb452b73fdd3a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Pre PLL pclk_dividera value range is from 1 to 31, but the default
value of register 0xe0 on 3229 is zero. To avoid div zero error,
we take the divider value as one.
[<c0110070>] (unwind_backtrace) from [<c010bcbc>] (show_stack+0x20/0x24)
[<c010bcbc>] (show_stack) from [<c040f56c>] (dump_stack+0x80/0xa0)
[<c040f56c>] (dump_stack) from [<c010bbf4>] (__div0+0x20/0x28)
[<c010bbf4>] (__div0) from [<c040d62c>] (Ldiv0_64+0x8/0x18)
[<c040d62c>] (Ldiv0_64) from [<c043f310>] (inno_hdmi_rk3228_phy_pll_recalc_rate+0x104/0x114)
[<c043f310>] (inno_hdmi_rk3228_phy_pll_recalc_rate) from [<c043efac>] (inno_hdmi_phy_clk_recalc_rate+0x30/0x3c)
[<c043efac>] (inno_hdmi_phy_clk_recalc_rate) from [<c0980c00>] (clk_register+0x438/0x64c)
[<c0980c00>] (clk_register) from [<c0980e68>] (devm_clk_register+0x54/0x94)
[<c0980e68>] (devm_clk_register) from [<c0440028>] (inno_hdmi_phy_probe+0x24c/0x378)
[<c0440028>] (inno_hdmi_phy_probe) from [<c0566424>] (platform_drv_probe+0x60/0xac)
[<c0566424>] (platform_drv_probe) from [<c05645bc>] (driver_probe_device+0x120/0x2a8)
[<c05645bc>] (driver_probe_device) from [<c05647bc>] (__driver_attach+0x78/0x9c)
[<c05647bc>] (__driver_attach) from [<c0562a28>] (bus_for_each_dev+0x84/0x98)
[<c0562a28>] (bus_for_each_dev) from [<c05640d0>] (driver_attach+0x28/0x30)
[<c05640d0>] (driver_attach) from [<c0563c5c>] (bus_add_driver+0xdc/0x1f8)
[<c0563c5c>] (bus_add_driver) from [<c056533c>] (driver_register+0xac/0xf0)
[<c056533c>] (driver_register) from [<c0566364>] (__platform_driver_register+0x40/0x54)
[<c0566364>] (__platform_driver_register) from [<c122af4c>] (inno_hdmi_phy_driver_init+0x18/0x20)
[<c122af4c>] (inno_hdmi_phy_driver_init) from [<c0101ad4>] (do_one_initcall+0x114/0x1c8)
[<c0101ad4>] (do_one_initcall) from [<c1200ef0>] (kernel_init_freeable+0x1ac/0x280)
[<c1200ef0>] (kernel_init_freeable) from [<c0c5e4c8>] (kernel_init+0x18/0x11c)
[<c0c5e4c8>] (kernel_init) from [<c0107550>] (ret_from_fork+0x14/0x24)
Change-Id: Ib61fbd87547d3316e9ed5b564e291b6c15d93cdd
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch fix the following clang warning:
[clang]drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1255:3:
warning: Value stored to 'delay' is never read
Change-Id: I8c70975e1bc2b24a78d0934ccefc9d67fe3a5da9
Signed-off-by: William Wu <william.wu@rock-chips.com>
In dwc_otg_hcd_endpoint_disable(), the hc_regs is initialized
to NULL, but never assign a host channel reg address to it,
so the chdis operation can't be handled for ever.
This patch gets a host channenl reg address for hc_regs via
qh->channel->hc_num.
Change-Id: I5917df1975000876d28868ed51e218489ed3d209
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reduce the otg schedule delay time from 6s to 1s to do
the first time usb charger detection earlier when power
on system with usb cable connect to PC USB. Because the
usb connection willed be disconnectted during usb charger
detection.
And the patch also makes the phy detect the usb disconnetion
more quickly after usb cable plug out.
Change-Id: I9b55317ab3592f517fdf590fea85c4ed403bbd8d
Signed-off-by: William Wu <william.wu@rock-chips.com>
Open pre-emphasize in non-chirp state for rk322x USB
PHY0 otg port to increase HS slew rate.
Change-Id: Ia565746286a750a251619a83cbbead99c0ddecbd
Signed-off-by: William Wu <william.wu@rock-chips.com>
When NAND FLASH reads and writes with UECC, it may lose data.
Add a additional reading process to restore the data.
Change-Id: I08edc0f9f7867266e4e620c463b54f7813f66602
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>
When playing secure video, you need to interact with secure OS.
The interaction to secureOS must be a physical continuous memory,
so CMA needs to be used, and now CMA is not enough and 32M is
enough.
Change-Id: Ie665152808a048045e702b3e0e9d9137f30975b5
Signed-off-by: Rimon Xu <rimon.xu@rock-chips.com>
except rk3368 and rk3328 lineflag1 number should be set before last
active line 1000us, other platform lineflag1 number should be
set at the last active line.
Change-Id: I4598ae79f437e180c4de261894f09b421b473572
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
It has proved the controller has a potention broken state with a DTO
interrupt comes while the data payload is missing, which was not covered
by current software state machine. Add a xfer timer to work around
this buggy behaviour introduced by broken design.
Change-Id: I5019c5ba0cdeb59adcdd3a5231a2000b448762bc
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
RK3328 hdmi phy introduces an irq to detect ESD status
of TMDS link. If irq is triggered, it is need to reset
pdata_en signal.
Change-Id: I6190d57d3b4f7c4f6791e1204cb9d8a99da988e2
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
For those sub modules that have shadow registers in core isp, if
CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT of isp ctrl is disabled, the
new parameters will not be updated to shadow registers automatically.
BUG=b:36227021
TEST=scarlet can preview, LSC data table can be switched.
Change-Id: I804ddfc45b3c2fca9a6f51627af4264a25075070
Signed-off-by: ZhongYiChong <zyc@rock-chips.com>
Change-Id: I801f49e5b9ff2ec30cfe2cf821904b61174226d5
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
LSC data table size is 17x17, but when configuring data to ISP,
should be aligned to 18x17. That means every last data of last
line should be filled with 0, and not filled with the data of
next line.
BUG=b:36227021
TEST=scarlet can preview.
Change-Id: I5e923529429a1c60efff3827e594f32db7112c1f
Signed-off-by: ZhongYiChong <zyc@rock-chips.com>
Change-Id: Ib7805802fe616635c524ce2b17812cde3012b81a
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
This sorts out the locks in isp_stats.c to fix the warning of
new work queued when workqueue is draining.
BUG=b:36227021
TEST=camera recording stress on Dru, check not wq timeout
Change-Id: I83597dd6764c7fea861e7e5a2ca4614e074c9821
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Change-Id: I5fdc9b1e9913aa1286d70e3342f63008d5b140a0
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Fix the memleak of alloc_ctx which is allocated twice and
doesn't cleanup properly.
BUG=b:71686724
TEST=check the kmemleak scan result
Change-Id: I17d15bf69bcdb33bb2cf6d446316d268a0df1e96
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Change-Id: I9a7e821b2d08c008a6a5a463953281ddee2ba245
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Split the Rockchip ISP MIPI DPHY as a standalone driver.
This fix the error of rockchip isp1 and mipi_dphy_sy when
building as modules, "multiple definition of `init_module'".
Since the
commit 4aa8d9814f21 ("CHROMIUM: media: rockchip/isp1: fixup for different media/v4l API")
merged, this patch also removes the BROKEN flag in
commit 58d5a7a7ca76 ("CHROMIUM: Mark Rockchip ISP1 driver as BROKEN")
BUG=b:36227021
TEST=make allmodconfig
Change-Id: I7016842bbc97820d260c3200d25cb10b62ba903d
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/851556
Reviewed-by: Ricky Liang <jcliang@chromium.org>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
VIDEO_ROCKCHIP_ISP_DPHY_SY part is not included
Change-Id: I8ec9c6af5491511ff88669dbbb302b60f3d43d11
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
If uboot used the kernel dtb, need to enable the recovery key.
Change-Id: I5cc4ad22cc143b4aec04f5e75a5bd9727b208978
Signed-off-by: David Wu <david.wu@rock-chips.com>
Under the following conditions, phy will be abnormally enabled.
1. HDMI is enabled in uboot.
2. disabled/bridge_is_on/phy.enabled/mc_clkdis were updated to
work when probe.
3. HDMI is disconnected.
4. drm_helper_probe_single_connector_modes update connector->status
to disconnected and power off phy by dw_hdmi_update_power. But the
polled type of HDMI is DRM_CONNECTOR_POLL_HPD, output_poll_execute
will not process this disconnection, and dw_hdmi_bridge_disable is
not called, hdmi->disabled is still false.
5. vop will be switch to Tv encoder, and dclk is 27MHz.
6. HDMI is connected.
7. dw_hdmi_update_power is called in dw_hdmi_irq, for hdmi->disabled
is false, then phy is powered up with parameter of 27MHz, and
bridge_is_on is set to on.
8. VOP switch to HDMI mode, set the new dclk rate.
9. dw_hdmi_bridge_enable is called, but the bridge_is_on is already on,
phy will not set again, still maintain the parameters that do not
conform to the new dclk rate.
This patch introduced an variable initialized to indicate hdmi is
initialized before probe, e.g. uboot. When power off hdmi, initialized
and disabled is updated.
Change-Id: I163967ac02e7f29ab586acbfd25d5a15679470c8
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
