This patch can help us to fix pop after wake up via VAD,
and enable 'rockchip,no-deep-low-power' on all of
rk3308-evb, not only amic boards.
Change-Id: I07f4674dd8c7fbd400b3c9b265fbaec6bfb5829e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
It doesn't support 400MHz, but support 420MHz.
Change-Id: Ife31469307912f83919b02b532acde91cc0f19ce
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
In order to support 420MHz for gpu and 125MHz, 50MHz for gmac.
Change-Id: I2b0e3edbf08850555c5bd4bc1d063c8923d54bda
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This driver is modified to support RK1808 SoC.
Change-Id: Id622e126936a242f3dfbab94b0e7c7818b41f9ae
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
According to a description from TRM, add all the power domains
Change-Id: Id8c4af687c877e206f8ce08416dcb4e41a78ce46
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RK1808 SoC has an usb 2.0 comb phy with one otg-port and one
host-port. This patch adds port configurations for them.
Change-Id: Id4d117929ec0e327c8f2cc1a06d4caaa2d584f06
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add usb 2.0 host controller nodes, usb 3.0 otg controller
node, and usb 2.0 phy nodes for rk1808 SoC.
Change-Id: Icb23e3d1b929091b62824bba6f41ffb4ab262f69
Signed-off-by: William Wu <william.wu@rock-chips.com>
Support rockchip,rk1808-usb2phy-grf for rk1808 board.
Change-Id: I9f3cc8300bf2653689c07734b81bcf7ff9aac4eb
Signed-off-by: William Wu <william.wu@rock-chips.com>
Support rockchip,rk1808-dwc3 for rk1808 board.
Change-Id: I68d9233e8cdf4704b54eb1fe2f17baf43ab6caf5
Signed-off-by: William Wu <william.wu@rock-chips.com>
When the pin is set as an iomux value that is outside its range,
it should return a failure, otherwise it may be overwritten with
incorrect value.
Change-Id: I381d9f5bf6f4bfa7d0512350e6b051bebf513d3e
Signed-off-by: David Wu <david.wu@rock-chips.com>
It looks better that handle the hight pass filter (HPF)
on the user space, therefore, disable it by codec.
By the way, add HPF dapm controls if someone need to
enable HPF cut-off.
Change-Id: Id8d5f4f84a8ad9909d6aa35c484e955ab92bffed
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We find an usb phy 480MHz clk prepare fail issue on PX30/RK3326
platforms with RK819 PMIC. On PX30/RK3326 platforms, we set the
usb480m clk to critical because GPU 480M is from usb480m and the
source clocks should be always on. And the usb phy 480MHz clk is
parent of usb480m clk, so the clk framework will prepare the usb
phy 480MHz clk when register it.
This logic works well if the usb phy probe only once. But if the
usb phy needs to probe twice or more because of some reasons (e.g.
fail to get vbus regulator from RK819), the usb phy 480MHz clk will
be unregistered and registered again, however, the clk framework
doesn't prepare the usb phy 480MHz clk except the first time register
operation. So we move the 480MHz clk register to the end of probe,
and make sure only register it once.
Change-Id: If69378b49035746a7c0107c6a363c4d91dfc15e5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
We need to insert some delay after enabling ADC current
and waiting ADCs are stable for BIST mode mainly.
Change-Id: Ib3cdc6aa36f8674ba8d8defadb47baac72f4745e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
If we playback before capture, the loopback will be
switch to BIST SINE mode by other ADC grps. Let's
fix it.
Change-Id: Ib18a32d87dfed4343edc439bd5c705295eca06f3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Dues to the broken ADC state, it may miss reset ADC digital
register and bring long time (~80ms) unstable and invalid
data at next recording.
Change-Id: Ibf516c054cab99536a4fa3b5fd82f52810352420
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch fixup wrong format if property missing.
Change-Id: I77a86c97b1526fa11a819ad0f2daca803e22ee7f
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
There's an u64 to int convert which may cause overflow.
Change-Id: I7feb46e501828666353506c37a1f35db39ff45f7
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
rkvdec dev status may wrong after irq, this may cause
next frame dec fail. so must add soft reset after irq
Change-Id: I8649206f353f5c3004b09f1255b50258afff1974
Signed-off-by: Siyong Chen <sayon.chen@rock-chips.com>
Cpu clock rate should be less than or equal to low rate when
change pll rate in boost module.
Change-Id: I53c4e66f06bba1e6a85920df0aaceb80176ab016
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
There are some configuration options for cpu boost, such as low
frequency, higt frequency, boost backup pll, and so on.
Change-Id: I35d65f05bbd5ef2a70e4a2e4637e7b4f9f67dda9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add constants and callback functions for the dwmac on rk1808 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Change-Id: I39a75b89cd17331bb4373b9b249ae206e1420e71
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch set attempts to new compatible for thermal founding
on RK1808 SoCs.
Change-Id: I133218cd958e0aabf711a5d22fe5e5da2fbd59ce
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
mkkrnlimg/resource_tool is build from source, don't use $(srctree)
on Makefile.
make modules when $(srctree) == $(objtree) otherwise build will
fail.
Change-Id: I7824d0e9cb60ca40925c4047a203242c6e50505d
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
mkkrnlimg/resource_tool is build from source, don't use $(srctree)
on Makefile.
make modules when $(srctree) == $(objtree) otherwise build will
fail.
Change-Id: If8461a30d450aef089ae7db5f5851d4837e7c303
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
