meaningful for non-atomic drivers, for atomic drivers this is
forced to be NULL.
Change-Id: Ic3591c4f4c3ee6de53f89d0b4f230829b1ed056d
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
1.Filling the HDMI AVI infoframe quantization range information.
2.If output is limited enable color space conversion to convert.
Change-Id: I75f666424f00f3f6ec695047f7851824e89cd1a5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Under the following conditions, phy will be abnormally enabled.
1. HDMI is enabled in uboot.
2. disabled/bridge_is_on/phy.enabled/mc_clkdis were updated to
work when probe.
3. HDMI is disconnected.
4. drm_helper_probe_single_connector_modes update connector->status
to disconnected and power off phy by dw_hdmi_update_power. But the
polled type of HDMI is DRM_CONNECTOR_POLL_HPD, output_poll_execute
will not process this disconnection, and dw_hdmi_bridge_disable is
not called, hdmi->disabled is still false.
5. vop will be switch to Tv encoder, and dclk is 27MHz.
6. HDMI is connected.
7. dw_hdmi_update_power is called in dw_hdmi_irq, for hdmi->disabled
is false, then phy is powered up with parameter of 27MHz, and
bridge_is_on is set to on.
8. VOP switch to HDMI mode, set the new dclk rate.
9. dw_hdmi_bridge_enable is called, but the bridge_is_on is already on,
phy will not set again, still maintain the parameters that do not
conform to the new dclk rate.
This patch introduced an variable initialized to indicate hdmi is
initialized before probe, e.g. uboot. When power off hdmi, initialized
and disabled is updated.
Change-Id: I163967ac02e7f29ab586acbfd25d5a15679470c8
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If hdmi is enabled in uboot and pluged out when booting kernel,
the hdmi phy is still enabled. It's better to disable it to
match the real status.
Change-Id: Ia1c5ede6499ee277d08c35a85c50e3257305f90f
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If hdmi plug in when kernel starting, hdmi may be without output.
Because the old criteria that to determine whether uboot logo is
on is hdmi phy pll locked and hdmi is connected. But in some
platform(such as rk3229), hdmi phy pll is locked even hdmi phy
is power down. In this case, the old criteria is unreliable.
So we add a new criteria that check Frame Composer register.If
the register value is not 0, we think that uboot logo is on,
hdmi has been setup.
Change-Id: Ifaa27030e5f5d551bec8f971694ff5d9c34a7c1d
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If hdmi is enabled in uboot, hdmi->disabled and bridge_is_on and
phy status need to be updated.
Change-Id: Ib21d894b673bf12b46a271c91d3e08fe7475ea89
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
If vop return error when showing kernel logo, connector atomic flush
will not be call, and mc_clkdis can not be updated.
This patch update mc_clkdis in the dw_hdmi_bind, when phy clock is
locked and HPD is connected.
Change-Id: I1498d787a993961fe75236c309ecc3c898d611a4
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
To avoid screen flash when updating CSC, we introduce connector
atomic_begin. Before flush crtc and connector, it's need to send
AVMUTE flag to make screen black, and clear flag after CSC updated.
AVMUTE -> Update CRTC -> Update HDMI -> Clear AVMUTE
Change-Id: Id47caac1e25fcce5a5aa7b879da4a6b9a9bab8a1
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
atomic_begin is used to prepare for update flush.
Change-Id: I1d3a2afaea4022c065bda2b4c0746464cc0c1303
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Introduce dw_hdmi_connector_atomic_flush to implement connector
atomic_flush.
Only when enc_in_encoding/enc_out_encoding/enc_in_bus_format/
enc_out_bus_format changed, dw_hdmi_setup is called.
Introduce previous_pixelclock/previous_tmdsclock/mtmdsclock to
determine whether PHY needs initialization. If phy is power off,
or mpixelclock/mtmdsclock is different to previous value, phy is
need to be reinitialized.
Change-Id: I1984fb188ba486de18f6d51b7a51320bbf2bc27d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
1.change SDA high level holding time to 3us.
2.when plug in,add timer to avoid unstable state.
Change-Id: Idc6faec710137ac9f8e589d75cbc1b85f7a45faf
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If a display support HDMI2.0, it must support SCDC or YCbCr420.
So we check the connector->scdc_present and mode->flags to
check the connected display is HDMI 2.0.
Change-Id: I3b868d43791089fcdef77f99ec90396553008b9a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
arm64 do not support earlyprintk, and use earlycon instead.
Change-Id: I089707eb69f6ad985fb4040248dc62d6ccd0dd78
Signed-off-by: Liang Chen <cl@rock-chips.com>
Fixed commit d45556ed94 ("soc: rockchip: power-domain: Add protection
for some special pd during startup") states.
If the pd is power down by default. but it's has keepon_startup flag,
need to power up it before pm_genpd_init.
(ie: PD is off by default on PX30 SOC)
Change-Id: I60e9a5385794ad73f7da86cf8a18aaeecc8bcc6b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If the system needs hold register values when system will reboot.
need to set only resetting pmic register for 817&809 forcedly.
Change-Id: Ib4b850c86ec3079cd7e374bc96460ee1532854a2
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Add support for the rk809 and rk817 regulator driver.
Their specifications are as follows：
1. The RK809 and RK809 consist of 5 DCDCs, 9 LDOs
and have the same registers for these components except dcdc5.
2. The dcdc5 is a boost dcdc for RK817 and is a buck for RK809.
3. The RK817 has one switch but The Rk809 has two.
The output voltages are configurable and are meant to supply power
to the main processor and other components.
Change-Id: Id652bcc749263bfb70dc9fe9490d56f10f7345d4
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Acked-by: Mark Brown <broonie@kernel.org>
[rebased on top of 5.2-rc1]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry picked from commit e444f6d68c)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RK809 and RK817 are power management IC chips for multimedia products.
most of their functions and registers are same, including the clkout
funciton.
Change-Id: Ie86ae58b47a3afc0fe298fdecf9e43d8cae232a9
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry picked from commit 8ed1440197)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RK809 and RK817 are power management IC chips for multimedia products.
Most of their functions and registers are same, including the rtc.
Change-Id: I090ac33f951b64f5c88e6defe67d1f50f8ffd4e5
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry picked from commit dc79054a64)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The function pointer pm_power_off may point to function from other
module (PSCI for example). If rk808 is removed, pm_power_off is
overwritten to NULL and the system cannot be powered off.
This patch checks if pm_power_off points to a module function.
Change-Id: I00de90d1f5f1cf6587167e59d7e577f484e1fc8c
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry picked from commit 7630499464)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The RK809 and RK817 are a Power Management IC (PMIC) for multimedia
and handheld devices. They contains the following components:
- Regulators
- RTC
- Clocking
Both RK809 and RK817 chips are using a similar register map,
so we can reuse the RTC and Clocking functionality.
Most of regulators have a some implementation also.
Change-Id: I7bc906a41c49e3f1552cf19f1d5fb75b5b8957b3
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
(cherry picked from commit 586c1b4125)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
if there are lots of irqs for a device and the register addresses for these
irqs is continuous, we can use this macro to initialize regmap_irq value.
Change-Id: If358af414c98951363315510b1d23748ba0683e0
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 43fac3238c)
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Now we set the load of fixed rate scene to 100%, it isn't accurate,
it is better to update stats if auto freq is enabled.
Change-Id: I7de2c5f0b218cbeb32340bf3287cee0565773785
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
If the platform supports yuv420, set ycbcr_420_allowed to true.
Change-Id: I963b35b1e243f3267a3237c82120e6fe826850d5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Now the DW-HDMI Controller supports the HDMI2.0 modes, enable support
for these modes in the connector if the platform supports them.
We limit these modes to DW-HDMI IP version >= 0x200a which
are designed to support HDMI2.0 display modes.
Change-Id: I719a138151b1fa2e16941d2f3ac2d8a71bba4a99
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
(am from https://patchwork.kernel.org/patch/282372/)
If sink doesn't support YCBCR420 deep color, we return default
8bit.
In YCBCR420 mode, tmdsclock is half of RGB444 mode.
Change-Id: Ie3a1f8ca4bbe4b3bae5d7c9ea823fc798721a73a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch is based on https://patchwork.kernel.org/patch/9801533,
add the drm property "hdmi_output_format", the possible value
could be:
- RGB
- YCBCR 444
- YCBCR 422
To handle various subsampling of YCBCR output types, this property
allows two special automatic cases:
- DRM_HDMI_OUTPUT_YCBCR_HQ
This indicates preferred output should be YCBCR output,
with highest subsampling rate by the source/sink, which
can be typically:
- ycbcr444
- ycbcr422
- ycbcr420
- DRM_HDMI_OUTPUT_YCBCR_LQ
This indicates preferred output should be YCBCR output, with
lowest subsampling rate supported by source/sink, which can be:
- ycbcr420
- ycbcr422
- ycbcr444
Default value of the property is set to 0 = RGB, so no changes if you
don't set the property.
Change-Id: Ie4a98ba91c8285a2e8f1ec7832d73183ad57665e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch introduce a drm property hdmi_output_depth to
get/set HDMI color depth, the possible value could be
- Automatic
This indicates prefer highest color depth, it is
30bit on rockcip platform.
- 24bit
- 30bit
The default value of property is 24bit.
The max_tmds_clock is 0 on some display device, we think it's
max_tmds_clock is 340MHz.
If tmdsclock > max_tmds_clock, real output color depth fallback
to 24bit.
Change-Id: I666ac85d1ce5e73af31251eae324d1a6ae00b31e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Set HDMI controller input/output bus format according to vop bus format.
Change-Id: Ib669ee6b0ea586410c715518d0bc9c55f5a52a50
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
According to HDMI spec 1.4, YCbCr422 is also 36-bit mode, so
we remove the override of color format when parsing hdmi deep
color info. And record hdmi YCbCr444 deep color info in
edid_hdmi_dc_modes.
The edid_hdmi_dc_modes should be clean up when parsing EDID.
Change-Id: Ic5bd3ff5e50b37f04ed4a0688be68bd8259e5af0
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
