RK816 ldo write mask bit is always 1 after setting finished, but
when system start, the write mask bit is 0 even enable bit is 1.
So that rk816 regulator driver '.is_enabled()' returns disabled state
even the ldo is power on when system start, we need to initial write
mask bit as 1.
Change-Id: I8b5b83f33d668e4bdd1f96d77208931d25b8f6d9
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Without this patch, when sample resistor is 20mR, battery charge
current is fixed in 1000mA which is lower than user configure at
the most time.
Change-Id: Idc93f5becfefd55992ea791a65c565feb313b779
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
The bootloader voltage is greater than the max voltage set by
opp-microvolt. This resulting in:
[ 1.949575] cpu cpu0: scale_rate=1008000000
[ 1.949822] vdd_arm: Restricting voltage, 1200000-1175000uV
[ 1.949854] vdd_arm: Restricting voltage, 1200000-1175000uV
[ 1.949874] cpu cpu0: _set_opp_voltage: failed to set voltage (1000000 1000000 1175000 mV): -22
[ 1.949889] cpu cpu0: failed to set volt 1000000
Change-Id: Id9bd6f3c7f4bf8ad2bd8a1a798ea4f8eed6b18b2
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
Need to keep the vdd_arm voltage set by the bootloader until all consumer
complete the initialization of the frequency voltage constraint.
The previous kernel was using the property regulator-init-microvolt.
The commit 8726e76f58 ("Revert "regulator: of: Use regulator-init-microvolt as early minimum"")
change it to regulator-early-min-microvolt property.
Change-Id: If86994dd3f6a845efbde6cbadfbd73e3572a544b
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
Add extension unit descriptor for uvc. Support 3
controls in this extension unit. The rockchip IQ
tool use it to transfer vendor specific control
data.
Change-Id: I219e12616629bc75548b30ce63d46136aeac6561
Signed-off-by: William Wu <william.wu@rock-chips.com>
use HIWORD_UPDATE(val, 0xffff, 0) instead of val | CRYPTO_WRITE_MASK_ALL
to make code more clearly.
Change-Id: I9a27914911e09ae2395577ac51bacfa96a958ec8
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
This module should do nothing on system suspend and resume,
otherwise clk_bulk_disable is called when clk is not enabled,
and that will cause core dump.
Change-Id: Ib89b0dfd831c225ff852c35b8d25221453c5679d
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Remove enable/disable ALC/AGC, and put their into
dapm controls.
Change-Id: I669347caab58470d9a6b6d017c70553fbb629426
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
It may that there is many registers need to be operated,
For more flexibility, we can use e->reg to indicate ADC
grps.
Change-Id: I701a151102e499bd0b5c31014039268ff4e5bfda
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Add dts file to support rk1808 evb rev10, which powered by
rockchip pmic rk809.
Change-Id: Ifbec2b70c5c0cabae24fe47113a1b1c39472b457
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
It looks like that we still keep the resetting ADC digital
and avoid the broken noise for loopback at starting.
And, remove adc_path_state which is not used now.
Change-Id: I514692b1bbb4bad1f0ce5413ca5891fd41083549
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The main description for rk3308b is as follows:
- Old iomux multiplexing extension;
- GRF_SOC_CON5 register add some bits;
- Newly added GRF_SOC_CON13/15 register.
Change-Id: I94bfcae5387aceae14895f1cafa0bfea51bf8b63
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch fixup the lost vad activity frames count in the
first round dma xfer.
Change-Id: I72c1e5a9aeefc4966741b1fbf9c9e4d551cacfab
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch recaculate the hw pointer to make the vad data
available and submit the residue dma buffer requests in
single xfer mode for the first round, and then cyclic xfer
mode for normal.
Change-Id: I27c1d6e32cfcac74ae53bb151da859cd4325517b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch add support for memcpy with padding size.
just like extend vad 6ch to 8ch buffer, so the padding
is needed.
Change-Id: Ie9777b2856d556d4934bce6e850dae9b27b078db
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Kingston DataTraveler 3.0 sometime would be disconnected
or not be enumerated successfully by xHCI controller when
LPM was enabled.
This patch adds an USB_QUIRK_NO_LPM quirk for this device.
Change-Id: I8ffa8d46ee242ab9665ce70565df7718b20ca87c
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch can help us to fix pop after wake up via VAD,
and enable 'rockchip,no-deep-low-power' on all of
rk3308-evb, not only amic boards.
Change-Id: I07f4674dd8c7fbd400b3c9b265fbaec6bfb5829e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
It doesn't support 400MHz, but support 420MHz.
Change-Id: Ife31469307912f83919b02b532acde91cc0f19ce
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
In order to support 420MHz for gpu and 125MHz, 50MHz for gmac.
Change-Id: I2b0e3edbf08850555c5bd4bc1d063c8923d54bda
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This driver is modified to support RK1808 SoC.
Change-Id: Id622e126936a242f3dfbab94b0e7c7818b41f9ae
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
According to a description from TRM, add all the power domains
Change-Id: Id8c4af687c877e206f8ce08416dcb4e41a78ce46
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RK1808 SoC has an usb 2.0 comb phy with one otg-port and one
host-port. This patch adds port configurations for them.
Change-Id: Id4d117929ec0e327c8f2cc1a06d4caaa2d584f06
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add usb 2.0 host controller nodes, usb 3.0 otg controller
node, and usb 2.0 phy nodes for rk1808 SoC.
Change-Id: Icb23e3d1b929091b62824bba6f41ffb4ab262f69
Signed-off-by: William Wu <william.wu@rock-chips.com>
Support rockchip,rk1808-usb2phy-grf for rk1808 board.
Change-Id: I9f3cc8300bf2653689c07734b81bcf7ff9aac4eb
Signed-off-by: William Wu <william.wu@rock-chips.com>
Support rockchip,rk1808-dwc3 for rk1808 board.
Change-Id: I68d9233e8cdf4704b54eb1fe2f17baf43ab6caf5
Signed-off-by: William Wu <william.wu@rock-chips.com>
When the pin is set as an iomux value that is outside its range,
it should return a failure, otherwise it may be overwritten with
incorrect value.
Change-Id: I381d9f5bf6f4bfa7d0512350e6b051bebf513d3e
Signed-off-by: David Wu <david.wu@rock-chips.com>
It looks better that handle the hight pass filter (HPF)
on the user space, therefore, disable it by codec.
By the way, add HPF dapm controls if someone need to
enable HPF cut-off.
Change-Id: Id8d5f4f84a8ad9909d6aa35c484e955ab92bffed
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We find an usb phy 480MHz clk prepare fail issue on PX30/RK3326
platforms with RK819 PMIC. On PX30/RK3326 platforms, we set the
usb480m clk to critical because GPU 480M is from usb480m and the
source clocks should be always on. And the usb phy 480MHz clk is
parent of usb480m clk, so the clk framework will prepare the usb
phy 480MHz clk when register it.
This logic works well if the usb phy probe only once. But if the
usb phy needs to probe twice or more because of some reasons (e.g.
fail to get vbus regulator from RK819), the usb phy 480MHz clk will
be unregistered and registered again, however, the clk framework
doesn't prepare the usb phy 480MHz clk except the first time register
operation. So we move the 480MHz clk register to the end of probe,
and make sure only register it once.
Change-Id: If69378b49035746a7c0107c6a363c4d91dfc15e5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
We need to insert some delay after enabling ADC current
and waiting ADCs are stable for BIST mode mainly.
Change-Id: Ib3cdc6aa36f8674ba8d8defadb47baac72f4745e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
