This adds support for the BOE Corporation MV270QUM-N10 27"
eDP(HBR2, 5.4Gbps) UHD TFT LCD panel, which can be supported
by the simple panel driver.
Change-Id: Ib7df60a7c9a5cd4755a67bedef35a95bcc16a498
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
when power invert and power on:
->loader_protect[on]->disable regulator(ref count is 0)
-> panel_simple_prepare[on]->disable regulator(ref count is 0)
->loader_protect[off]->enable regulator(ref count is 1)
->suspend->enable regulator(ref count is 2)
->resume->disable regulator faild(ref count is 1)
Fixes: 7a91ba36d80 ("drm/panel: panel: add power-invert for some special hardwre")
Change-Id: I43f1cef2410316faec24238cd3f8d2bc1fe38335
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
if power-invert exist the panel power need to disable ldo when
power on and enable ldo when power off otherwise it's opposite.
example:
panel {
...
power-invert;
...
};
Change-Id: Ida5718d01044873cdd7c753c4e8b872dc1e52099
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This adds support for the BOE Corporation MV238QUM-N20 23.8"
eDP(HBR2, 5.4Gbps) UHD TFT LCD panel, which can be supported
by the simple panel driver.
Change-Id: I5ec47bf4864899ab437a8aea4fa0d58d338b709a
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This adds support for the LG Corporation LM238WR2-SPA1 23.8"
eDP(HBR2, 5.4Gbps) UHD TFT LCD panel, which can be supported
by the simple panel driver.
Change-Id: I586684ba893be54fbf664a8fa4dad0fe5eb999a0
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This adds support for the LG Corporation LM270WR3-SSA1 27"
eDP(HBR2, 5.4Gbps) UHD TFT LCD panel, which can be supported
by the simple panel driver.
Change-Id: I542cfe03325a43bc56d7b1c7a62ae7b6aaabc751
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
U8_MAX payload length can meet most requirements
Change-Id: I77e5780bde72b4229ab36d961dc7498f7c78a468
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
copy include/uapi/linux/media-bus-format.h to include/dt-bindings/display/media-bus-format.h
So we can use media bus format on device-tree.
Change-Id: I8f63856c4d61c77958c24cd5a4436050b85a093c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The INNOLUX N125HCE-GPA is a 12.5' TFT Liquid Crystal Display NB module
with LED Backlight unit and 30 pins eDP interface. This module supports
1920x1080 FHD mode and can display 16.7M colors.
Change-Id: I72318ac3317cd03e2301a1cab61cf126cd2a401b
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
The AUO B125HAN03.1 panel is a 12.5' FHD 16:9 Color TFT-LCD
and 30 pins eDP interface.
Change-Id: Ic2be5f1d5a3e25d805e0752c1c1fad0decc4f2d0
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
The BOE NV125FHM-N73 panel is a 12.5' FHD 16:9 Color TFT-LCD
and 30 pins eDP interface.
Change-Id: Idc15fb7126bf778fd23a766b01c2d5cf9760d4f3
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Since commit (f6972eb FROMLIST: drm/panel: add of display
timing support), when panel has no device-tree timing, would always
get noise message:
[ 8.742157] /lvds_panel: could not find display-timings node
[ 8.747878] /lvds_panel: no timings specified
Change-Id: I9104b3017faa837807a09c21d0f948e499827ad9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
When enable display on loader, init gpio would change gpio status,
that would make screen flash,
Change-Id: I4b69a8d3d83c5bef09014c2134abaee6522a7046
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
We want add display support on loader, share the same timing
with kernel side, but the timing is hide into kernel code,
can't be share, avoid config twice display timing, add device-tree
display timing support would be good idea.
With this patch, loader and kernel can share same timing from
device node.
Cc: Thierry Reding <thierry.reding@gmail.com>
Change-Id: I6c1ee6ad0194e242035e2f11589d86fdb363b80a
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9238727)
The AUO B101EW05 panel is a 10.1" 1280(RGB)x800 WXGA TFT-LCD panel,
connected using LVDS interfaces
Change-Id: Ic67fe5793a975b585cecfb8da02e81cd9fa6346f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Chunghwa CLAA070WP03 is 7” color TFT-LCD module composed of LCD panel,
LVDS driver ICs, control circuit and backlight. This module supports
800x1280 mode.
Change-Id: I6a6339ad25664e2e47fc0e0de5c079db3494bd25
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.
Change-Id: Ib42185ffce772160133a3edf3c3cf61bff4b85c5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201799/)
The Samsung LSN122DL01-C01 is an 12.2" 2560x1600 (WQXGA) TFT-LCD panel
connected using eDP interfaces.
Change-Id: I3c2208fc45b53b0fab328fcb9ba204f610a9f9f6
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.
Change-Id: I3a279ff9e4dde421832e2f9fe8152ddfbadab2ae
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel
connected using four DSI lanes. It can be supported by the simple-panel
driver.
Change-Id: I4fe03fc830332e60997e98b24550801827692501
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit c8521969de)
An spi_driver does not need to set an owner, it will be populated by the
driver core.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
The LG4573 is used on the LG LCD LB043WV2-SD01, an industrial 4.3" TFT
panel with SPI control interface.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add support for the Okaya RS800480T-7X0GP to the DRM simple panel
driver.
The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel
LCD interface. It supports pixel clocks in the range of 30-40 MHz.
This panel details can be found at:
http://boundarydevices.com/product/7-800x480-display/
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM
simple panel driver.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com>
Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[treding@nvidia.com: add .bpc field for panel]
Signed-off-by: Thierry Reding <treding@nvidia.com>
The AUO B080UAN01 is an 8.0" WUXGA TFT LCD panel connected using four
DSI lanes. It can be supported by the simple-panel driver.
Signed-off-by: Thierry Reding <treding@nvidia.com>
According to the data sheet, the minimum horizontal blanking interval
is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
minimum working horizontal blanking interval to be 60 clocks.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The bus format both specifies the bpc and the way the individual bits get
serialized into the 7 LVDS timeslots.
While the is only one standard mapping for 6 bpc and so the driver could
infer the bit mapping from the bpc alone, there are more options for the
8 bpc case which makes specifiying the bus format mandatory.
To keep things consistent across panels and to set a precedent for new
panel additions add the proper bus format.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The likelihood of getting a large number of panel drivers from different
vendors is quite high. Add a prefix to the two existing Samsung panel
drivers to set a guideline for future patch submissions. Using vendor
prefixes consistently should allow a cleaner organization of the tree.
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch adds the bus_format field to the HSD100PXN1 panel structure.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add support for the Hannstar HSD100PXN1 to the DRM simple panel driver.
The HSD100PXN1 is an XGA (1024x768) panel with an 18-bit LVDS interface.
It supports pixel clocks in the range of 55-75 MHz.
This panel is offered for sale by Freescale as a companion part to its'
i.MX5x Quick Start board and i.MX6 SABRE platforms with under the name
MCIMX-LVDS1.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
There's some useless padding in the struct spi_driver definition. Remove
it since it serves no useful purpose.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Both the Samsung LD9040 and Samsung S6E8AA0 panel drivers are missing
a const qualifier for their OF match tables. This data is static and
never changes, so can be read-only.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds support for the LG LB070WV8 7" 800x480 panel to the DRM simple
panel driver.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the
DRM simple panel driver.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges
additionally to the typical values for pixel clock rate (64.3-82 MHz)
and blanking intervals (54-681 clock cycles horizontally, 3-23 lines
vertically).
This patch replaces this panel's display mode with the display timing
information to describe acceptable timings. Since the HSYNC and VSYNC
are unused, the distribution between front porches, back porches, and
sync pulse lengths was chosen at will.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
