On some chip, HDMI post PLL is not stable when it's vco is 1080M,
but it work ok when vco is 270M. We use a efuse bit to distinguish
these chip.
Change-Id: I143363d67e60747ee52d405edace3ec611de3e6e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
LEDS_IS31FL32XX is a led driver IC used by rk3308 evb.
Change-Id: I77c8dcd379e72bd85bffcad5f0ec51bbaf876274
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Inno hdmi phy post pll is enabled by default on rk3228, it's need to
manual power down post pll if uboot logo is not shown.
Change-Id: I7ed4de2eae2d723f390dae44281281b9e81f4e1d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
There are many factors affecting the clock phase, including clock
rate, temperature, logic voltage and silicon process, etc. But clock
rate is the most significant one here, and the driver should be aware
of the change of the clock rate. As mmc controller need a fixed phase
after tuning was completed, at least before explicitly doing re-tune,
so this patch try to restore the clock phase by monitoring the event
of rate change.
Change-Id: Id1ccdfd2e8d4e2eb9f6a1923b3813138dbaf99f7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from https://patchwork.kernel.org/patch/10269525/)
aptina/imx/ov_camera_module.c:
Fix this warning: this if clause does not guard... [-Wmisleading-indentation]
Change-Id: I788d4d4d04dd2b0b7c41e1a041e9084c62b1975c
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
fix bug error log: "rockchip-i2s ff070000.i2s: fail to clear".
When the TX/RX have started, can not do 'clear operation'.
Change-Id: I83c2ac29412a37a5de02ed9d4be62716fe46678a
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
When kernel change print log uart port, optee should keep the same
with it. Kernel driver will tell optee the uart port id when
tee-supplicant starts up.
If fiq-debugger node is disabled, then id is set as 0xffffffff,
optee uart print is disabled.
Change-Id: Id0bc5428d244896fa95eb6a9c2f36bd3ff1248b7
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>
in addition,
resolve all the conflicts;
rename all the configs and macros that have a same name in midgard/;
fix a compiling error.
Change-Id: I5abc8c925049e087c59b66da57c82aac3092be71
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
we can power off the bandgap to reduce power consumption.
Change-Id: I7959e6f1d38a6abca70d6d904264668a19ace920
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This change adds usb otg/host controllers and related phy nodes
on rk3308 SoC.
Change-Id: I5fd3acc44614cc3fcb58eb269c2e559ea24ab0f1
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This change adds usb-phy support for rk3308 SoC and amend related
phy Documentation.
Change-Id: I953af94fb4d55d79ae1cba624a04fb4b84e019f6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit dc71e51944 ("usb: dwc2: make otg manage lowlevel
hw on its own") aimed to control the clk and phy power for
otg mode, but it also introduced lost of new problems, so we
revert it.
This patch only controls phy power for otg mode, it can fix
the dwc2 udc start fail issue with the following error log:
dwc2_hsotg_init_fifo: timeout flushing fifos (GRSTCTL=80000430)
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
bound driver configfs-gadget
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
Change-Id: Id6996aecab7f0aaaf12530b7a377144e23ef1667
Signed-off-by: William Wu <william.wu@rock-chips.com>
This reverts commit dc71e51944.
We found that this commit will cause at least three issue:
1. On RK3126C Tablet, plug in OTG cable and U disk first,
then power on the Tablet, the system will hang because
of dwc2 interrupt storm.
2. On RK3328-EVB, connect usb to PC first, then power on
the board, the system will hang because of dwc2 interrup
store.
3. On Linux system, the OTG Host mode can't detect U disk.
The root cause is that this patch will diable the controller
clk at the end of probe if OTG work as OTG mode, and only
enable the clk again in dwc2_hsotg_udc_start(). However,
the dwc2 interrupt is enabled in dwc2_hcd_init() during probe,
so the dwc2 interrupt maybe triggered but the interrupt pending
state can't be cleared because that the clk has been disabled.
This cause dwc2 interrupt storm problem.
On the other hand, for Linux system, it may config OTG work
as OTG mode, but it never calls dwc2_hsotg_udc_start() to
enable the controller clk becasue there is no gadget application.
So the clk never be enabled, and casue OTG Host mode fail
to detect the U disk.
Change-Id: Id3463225e0232de7078de1e9d39470a6d5e2cea4
Signed-off-by: William Wu <william.wu@rock-chips.com>
add devfreq and devfreq_cooling feature for gpio-fan and then
it can be used as thermal cooling device to support IPA thermal
policy.
Change-Id: I376faa485625ac41276df9bbac8188ea8d664b36
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
add support for rgb panel or rgb covert to other interface panel.
Change-Id: I190ce6e08d38f794ecabb863e0def5e74890f75a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
There are two clocks between armclk and pll_apll on px30,
but there may be only one clock on some Socs, so it will
get a error pll clock.
Change-Id: I34116a1ec824b884d3745082f3546cd9ab4c0d21
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
