This adds the necessary data for handling dmcfreq on the rk3328
Change-Id: If4cff5cc372f80b6776a7272a1bff54abef2cf33
Signed-off-by: CanYang He <hcy@rock-chips.com>
This adds the necessary data for handling dmcfreq on the rk3128.
Change-Id: I6aeae7103c1eaed0b4515d8d11863c4b190b6918
Signed-off-by: Liang Chen <cl@rock-chips.com>
Add dfi and dmc nodes in the device tree for the ARM rk3288 SoC.
To support ddr frequency scaling function, we need enable dmc and
dfi nodes.
Change-Id: Ib796c08c694e74e0da3319d2797e95aecf3e7e73
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Add dfi and dmc nodes in the device tree for the ARM64 rk3368 SoC.
To support ddr frequency scaling function, we need enable dmc and
dfi nodes.
Change-Id: I155b838a8773ff1842058bebb1ed2747ca8e2e0b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
To support ddr frequency scaling function, we need
enable dmc and dfi node.
Change-Id: I84ea6bff679365d86937ff10bcdf466ea31901fb
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.
Currently this driver sets up the latency allowance registers to the HW
defaults. Eventually an API should be exported by this driver (via a
custom API or a generic subsystem) to allow clients to register latency
requirements.
This driver also registers an IOMMU (SMMU) that's implemented by the
memory controller. It is supported on Tegra30, Tegra114 and Tegra124
currently. Tegra20 has a GART instead.
The Tegra SMMU operates on memory clients and SWGROUPs. A memory client
is a unidirectional, special-purpose DMA master. A SWGROUP represents a
set of memory clients that form a logical functional unit corresponding
to a single device. Typically a device has two clients: one client for
read transactions and one client for write transactions, but there are
also devices that have only read clients, but many of them (such as the
display controllers).
Because there is no 1:1 relationship between memory clients and devices
the driver keeps a table of memory clients and the SWGROUPs that they
belong to per SoC. Note that this is an exception and due to the fact
that the SMMU is tightly integrated with the rest of the Tegra SoC. The
use of these tables is discouraged in drivers for generic IOMMU devices
such as the ARM SMMU because the same IOMMU could be used in any number
of SoCs and keeping such tables for each SoC would not scale.
Acked-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
