take 1280x720@60Hz which pclk is 74.25Mhz as an example, the dsi
lane rate should set 445500 Kbps/lane(pclk x bpp = lane_rate x lanes)
when mipi work in no video burst pulse/event, therefore the PLL should
output the rate of Kbps/ksps level for normal display.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I63bf5717e2da521b7af18d88c906b86e30a71488
Also change UCLAMP_BUCKETS_COUNT to 20 copy form ANDROID-GKI.
Using the default setting 5 means the first bucket contains the
uclamp values from 0 to 19 (in percentage), in this case, if the
uclamp.min setting of a group is under 20, it will fall into this
bucket with other groups that have uclamp.min set to 0, which
increase the possibility of over boost. By setting the bucket
count to 20 will ease this situation, while a uclamp.min greater
than 4 will fall into a different bucket.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I982a81acc303374aaf8defc004d08dd635402771
Also change UCLAMP_BUCKETS_COUNT to 20 copy form ANDROID-GKI.
Using the default setting 5 means the first bucket contains the
uclamp values from 0 to 19 (in percentage), in this case, if the
uclamp.min setting of a group is under 20, it will fall into this
bucket with other groups that have uclamp.min set to 0, which
increase the possibility of over boost. By setting the bucket
count to 20 will ease this situation, while a uclamp.min greater
than 4 will fall into a different bucket.
Change-Id: Ibc6e1cb4358cfd6f9cda784b43d754545b893d7d
Signed-off-by: Liang Chen <cl@rock-chips.com>
Both DP and MIPI get pixelclk from dclk_out as follow:
DP: dclkx_out(DIV)->dpn_pixelclk(MUX)
MIPI:dclkx_out(DIV)->mipi_clk_src(MUX)->mipi_pixelclk(DIV)
When a video port coonect DP, it will calculate dclk rate first,
then dclk out rate, finally dp pixelclk rate. When a video Port
connect to MIPI it will calculate mipi_pixelclk rate first.
The different calculation method may get different dclk rate or
divider ratio. When a video port connect to a DP and MIPI, DP
or MIPI may get the wrong pixel rate. So they need use the same
method to calculate pixelclk.
When A video port connect DP and MIPI, the mipi_pixelclk
is set first, and set the mipi_pixelclk divide value. Then
dp_pixelclk is set, which will modify dclk_out divide value
and cause the mipi_pixelclk change.
So when calculate the mipi_pixelclk, we calculate the dclk_out
first to avoid the mipi_pixelclk be modified when DP set
dp_pixelclk.
For uboot logo display, Depend on commit from u-boot(branch:
next-dev):
(I6037e12d8b6 drm/rockchip: vop2: change dclk calculate method
for mipi)
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I53c3247ce1eb728dad7f480d86b65d3f922ab6d4
Change cpu dynamic-power-coefficient across EAS data.
Change-Id: I06e3d4e8e05d8c42d3d2de74c8369ba51c575e66
Signed-off-by: Liang Chen <cl@rock-chips.com>
dma_fd buffer has been mapped by cryptodev and does not need to
be mapped again.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: Ic28bebe3b169dfc4cb1fde4457122277f32294bf
CRYPTO V1/V2 do not support multi-threading, so it is necessary
to add a hold mechanism in Cryptodev to prevent abnormal consequences
caused by multi-threading calls.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: Ifd5ff6b102c81c8ac44c16f9689d5219c7fa5a56
CONFIG_LS_UCS14620 is used to enable light sensor ucs14620
which found on rk3588s tablet rk806 single board.
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: Ib824361aacd7cf44fb2125f151f85b590c793e2b
CONFIG_PS_UCS14620 is used to enable proximitily sensor ucs14620
which found on rk3588s tablet rk806 single board.
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: I94a8dd2a4d86f3f1feb201eeb2dc7b3d56601adc
The av1d node is register av1dec_bus not platform bus,
so it no need to set okay status.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Id5ab7c5bf8380221b663730596335e9bda1eb6b2
The av1d node is register av1dec_bus not platform bus,
so it no need to set okay status.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Change-Id: I9c88340d6542c497b3e4b24406db93bd60369fd8
Add common APIs to set read margin and set intermediate rate.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I8fb1d16f4ca1a9ec0ba80019197a73e56391c14c
In order to get target read margin and scmi clk earlier,
and it will also be used in later submissions.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I75bd79dc4963fa0dcc73d7c66a696e1cc0c177b7
In order to modify the logic, check whether the standby
function is supported by (*crtc_standby). And add the
universal function rockchip_drm_crtc_standby().
Replace vop2_standby() by rockchip_drm_crtc_standby() in
dsi2 driver.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I974780c441fe0e9a8a81f933b3070a727321b589
1. When iommu pagefault, hardware will stop and wait to deal with it.
in order to respond quickly, such as NVR, reset the hardware directly.
2. The iommu handle should be for the current device, not the queue.
and, the mpp_task_dump_hw_reg function is used to dump hardware register
info, it no relation for task.
3. In the mode of link-mode and multi-core, it cannot accurately get task
via queue->running_task, thereforce, it is not suitable to dump task
register here.
Change-Id: Ifed2cbc484997a07ed65c38c16062abe9b9aff81
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
1. for rk3588, it may hung for when bus error, then, it should
use sip reset.
2. before reset, it make sure that the clock is on.
Change-Id: I2dd1dc5c4cd273eb8678ceaa29b0e966828f50fd
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
rv1126 does not support VOP2, so add config options to
reduce memory usage.
./ksize.sh drivers/gpu/drm/
before ksize: 487941 Bytes
after kszie: 380303 Bytes
save about: 107628 Bytes
In addition, improve the format of space and tab, and remove
extra "depends on DRM_ROCKCHIP".
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I2b29a543a7e52e4e4b72112980e2c6dc6c6cce92
Add constants and callback functions for the dwmac on RV1106 soc.
As can be seen, the base structure is the same,.In addition, there is
an internal phy inside.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I5889a7dd8bdbbbf763a617c5d1aa525454006e39
