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Author SHA1 Message Date
Swapnil Jakhade
7a5ad9b4b9 phy: cadence: Sierra: Update single link PCIe register configuration 
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-11-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:09 +05:30
Swapnil Jakhade
36ce416330 phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation 
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-10-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:09 +05:30
Swapnil Jakhade
f1cc6c3f08 phy: cadence: Sierra: Check cmn_ready assertion during PHY power on 
Check if PMA cmn_ready is set indicating the startup process is complete.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-9-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:09 +05:30
Swapnil Jakhade
fa10517211 phy: cadence: Sierra: Add PHY PCS common register configurations 
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-8-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:09 +05:30
Swapnil Jakhade
8c95e17226 phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation 
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-7-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:08 +05:30
Swapnil Jakhade
1e902b2ae3 phy: cadence: Sierra: Add support to get SSC type from device tree 
Add support to get SSC type from DT.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-6-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:08 +05:30
Swapnil Jakhade
262303b929 dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode 
Add binding to specify Spread Spectrum Clocking mode used.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211223060137.9252-5-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:08 +05:30
Swapnil Jakhade
253f06c7b1 dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names 
Rename SSC macros to use generic names instead of PHY specific names,
so that they can be used to specify SSC modes for both Torrent and
Sierra. Renaming the macros should not affect the things as these are
not being used in any DTS file yet.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211223060137.9252-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:08 +05:30
Swapnil Jakhade
078e9e9211 phy: cadence: Sierra: Prepare driver to add support for multilink configurations 
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-3-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:08 +05:30
Swapnil Jakhade
c3c11d5534 phy: cadence: Sierra: Use of_device_get_match_data() to get driver data 
Use of_device_get_match_data() to get driver data instead of boilerplate
code.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-2-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 16:35:08 +05:30
Miaoqian Lin
399c91c3f3 phy: mediatek: Fix missing check in mtk_mipi_tx_probe 
The of_device_get_match_data() function may return NULL.
Add check to prevent potential null dereference.

Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20211224082103.7658-1-linmq006@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-27 15:58:03 +05:30
Ryuta NAKANISHI
898c7a9ec8 phy: uniphier-usb3ss: fix unintended writing zeros to PHY register 
Similar to commit 4a90bbb478 ("phy: uniphier-pcie: Fix updating phy
parameters"), in function uniphier_u3ssphy_set_param(), unintentionally
write zeros to other fields when writing PHY registers.

Fixes: 5ab43d0f86 ("phy: socionext: add USB3 PHY driver for UniPhier SoC")
Signed-off-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1640150369-4134-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-24 10:06:38 +05:30
Chunfeng Yun
33d18746fa phy: phy-mtk-tphy: use new io helpers to access register 
Use new helpers mtk_phy_clear/set/update_bits() to access registers

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20211218082802.5256-5-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-24 10:06:38 +05:30
Chunfeng Yun
9520bbf3cb phy: phy-mtk-xsphy: use new io helpers to access register 
Use new helpers mtk_phy_clear/set/update_bits() to access registers

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20211218082802.5256-4-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-24 10:06:37 +05:30
Chunfeng Yun
1371b9a563 phy: mediatek: add helpers to update bits of registers 
Add three helpers mtk_phy_clear/set/update_bits() for registers operation

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20211218082802.5256-3-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-24 10:06:37 +05:30
Chunfeng Yun
6f2b033cb8 phy: phy-mtk-tphy: add support efuse setting 
Due to some SoCs have a bit shift issue that will drop a bit for usb3
phy or pcie phy, fix it by adding software efuse reading and setting,
but only support it optionally for version 2/3.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20211218082802.5256-2-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-24 10:06:37 +05:30
Chunfeng Yun
c6d92a287a dt-bindings: phy: mediatek: tphy: support software efuse load 
Add optional property nvmem-cells and nvmem-cell-names to support
software efuse load, this helps to fix the efuse bit shift issue
on mt8195 etc.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20211218082802.5256-1-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-24 10:06:37 +05:30
Dmitry Baryshkov
2c91bf6bf2 phy: qcom-qmp: Add SM8450 PCIe1 PHY support 
There are two different PCIe PHYs on SM8450, one having one lane (v5)
and another with two lanes (v5.20). This commit adds support for the
second PCIe phy.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211218141754.503661-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-24 10:06:37 +05:30
Dmitry Baryshkov
3ba4c0a8f4 dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings 
There are two different PCIe PHYs on SM8450, one having one lane and
another with two lanes. Add support for second (gen4, two lanes) PHY.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211218141754.503661-2-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-24 10:06:37 +05:30
Peter Geis
42b559727a phy: phy-rockchip-inno-usb2: add rk3568 support 
The rk3568 usb2phy is a standalone device with a single muxed interrupt.
Add support for the registers to the usb2phy driver.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-23 16:54:48 +05:30
Peter Geis
ed2b5a8e6b phy: phy-rockchip-inno-usb2: support muxed interrupts 
The rk3568 usb2phy has a single muxed interrupt that handles all
interrupts.
Allow the driver to plug in only a single interrupt as necessary.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-23 16:54:48 +05:30
Peter Geis
e6915e1acc phy: phy-rockchip-inno-usb2: support standalone phy nodes 
New Rockchip devices have the usb2 phy devices as standalone nodes
instead of children of the grf node.
Allow the driver to find the grf node from a phandle.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-23 16:54:48 +05:30
Peter Geis
9c19c531dc phy: phy-rockchip-inno-usb2: support #address_cells = 2 
New Rockchip devices have the usb phy nodes as standalone devices.
These nodes have register nodes with #address_cells = 2, but only use 32
bit addresses.

Adjust the driver to check if the returned address is "0", and adjust
the index in that case.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-23 16:54:48 +05:30
Peter Geis
8eff5b9904 dt-bindings: phy: phy-rockchip-inno-usb2: add rk3568 documentation 
The rk3568 usb2phy node is a standalone node with a single muxed
interrupt.
Add documentation for it to phy-rockchip-inno-usb2.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211215210252.120923-3-pgwipeout@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-23 16:54:48 +05:30
Dmitry Baryshkov
107ba9bf49 phy: qcom-qmp: Add SM8450 PCIe0 PHY support 
There are two different PCIe PHYs on SM8450, one having one lane (v5)
and another with two lanes (v5.20). This commit adds support for the
first PCIe phy only, support for the second PCIe PHY is coming in next
commits.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211214225846.2043361-4-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-18 11:25:07 +05:30
Dmitry Baryshkov
9710b162c8 dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings 
There are two different PCIe PHYs on SM8450, one having one lane and
another with two lanes. Add DT bindings for the first one. Support for
second PCIe host and PHY will be submitted separately.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211214225846.2043361-3-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-18 11:24:41 +05:30
Vinod Koul
6ad102e05d phy: qcom-qmp: Add SM8450 USB QMP PHYs 
Add support for the USB DP & UNI PHYs found on SM8450. This is same as
the phy version used on SM8350 and sequences turned out to be same, so
use the same table from SM8350 for this as well.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211213131450.535775-3-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-16 12:06:01 +05:30
Vinod Koul
03eacc3c65 dt-bindings: phy: qcom,qmp: Add SM8450 USB3 PHY 
Add compatible string for USB QMP phy in Qualcomm SM8450 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211213131450.535775-2-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-16 12:06:01 +05:30
Vinod Koul
d8f0136919 dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SM8450 
Document the compatible string for USB phy found in Qualcomm SM8450 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211213131450.535775-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-16 12:06:01 +05:30
Vinod Koul
c8d09c7ebc phy: freescale: pcie: explicitly add bitfield.h 
kernel test robot complains about missing FIELD_PREP, so include
bitfield.h for that

drivers/phy/freescale/phy-fsl-imx8m-pcie.c:41:37: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
drivers/phy/freescale/phy-fsl-imx8m-pcie.c:41:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]

Reported-by: kernel test robot <lkp@intel.com>
Fixes: 1aa97b0022 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver")
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Link: https://lore.kernel.org/r/20211215060834.921617-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-15 20:50:43 +05:30
Richard Zhu
1aa97b0022 phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver 
Add the standalone i.MX8 PCIe PHY driver.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Link: https://lore.kernel.org/r/1638432158-4119-6-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-14 20:02:53 +05:30
Richard Zhu
b3b5516a6f dt-bindings: phy: Add imx8 pcie phy driver support 
Add dt-binding for the standalone i.MX8 PCIe PHY driver.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1638432158-4119-3-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-14 20:02:32 +05:30
Richard Zhu
f6f787874a dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy 
Add binding for reference clock PAD modes of the i.MX8 PCIe PHY.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1638432158-4119-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-14 20:02:32 +05:30
Colin Ian King
b156117aed phy: rockchip-inno-usb2: remove redundant assignment to variable delay 
Variable delay is being assigned to zero and the code falls through to
the next case in a switch statement that returns out of the function.
The variable is never read in this scenario and so the assignment is
redundant and can be removed.

Cleans up scan-build static analysis warning:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c:753:3: warning: Value
stored to 'delay' is never read [deadcode.DeadStores]

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Link: https://lore.kernel.org/r/20211211180054.525368-1-colin.i.king@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-14 14:45:07 +05:30
Horatiu Vultur
9d031a51b3 phy: lan966x: Remove set_speed function 
Remove the set_speed function and allow the driver to figure out the
speed at which needs to configure the serdes based on the interface type.

Fixes: 305524902a ("phy: Add lan966x ethernet serdes PHY driver")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20211211214717.1284306-1-horatiu.vultur@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-14 14:24:48 +05:30
Miaoqian Lin
16c57fff83 phy: ti: Use IS_ERR_OR_NULL() to clean code 
Use IS_ERR_OR_NULL() to make the code cleaner.

Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20211212142226.23674-1-linmq006@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-14 13:10:03 +05:30
Luca Weiss
918aaae300 dt-bindings: phy: qcom,qusb2: Add SM6350 compatible 
Add devicetree compatible for the usb phy on SM6350 SoC.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20211213082614.22651-5-luca.weiss@fairphone.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-14 13:08:26 +05:30
Miaoqian Lin
045a31b955 phy: tegra: xusb: Fix return value of tegra_xusb_find_port_node function 
callers of tegra_xusb_find_port_node() function only do NULL checking for
the return value. return NULL instead of ERR_PTR(-ENOMEM) to keep
consistent.

Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20211213020507.1458-1-linmq006@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-14 13:07:21 +05:30
Guo Zhengkui
e87f13c33e phy: qcom: use struct_size instead of sizeof 
Use struct_size() to get the accurate size of `clk_hw_onecell_data`
with a variable size array, instead of sizeof(data) to get the size
of a pointer.

Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com>
Fixes: f199223cb4 ("phy: qcom: Introduce new eDP PHY driver")
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211209032114.9416-1-guozhengkui@vivo.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-09 17:24:54 +05:30
Vinod Koul
15aa1f668c phy: qcom-qmp: Add SM8450 UFS QMP Phy 
SM8450 UFS seems to use same sequence as SM8350, so reuse the sequence
from SM8450. Add the new clock list for this phy and the new compatible

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Co-developed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Martin K. Petersen <martin.petersen@oracle.com>
Link: https://lore.kernel.org/r/20211201074456.3969849-4-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-07 17:28:55 +05:30
Vinod Koul
e04121ba1b dt-bindings: phy: qcom,qmp: Add SM8450 UFS phy compatible 
Document the UFS phy compatible for QMP UFS phy found in SM8450 SoC.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Martin K. Petersen <martin.petersen@oracle.com>
Link: https://lore.kernel.org/r/20211201074456.3969849-3-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-07 17:28:55 +05:30
Vinod Koul
07cc0fa49b scsi: ufs: dt-bindings: Add SM8450 compatible strings 
Document "qcom,sm8450-ufshc" compatible string. "qcom,sm8450-ufshc" is
for UFS HC found in SM8450 SoC.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Martin K. Petersen <martin.petersen@oracle.com>
Link: https://lore.kernel.org/r/20211201074456.3969849-2-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-07 17:28:54 +05:30
Horatiu Vultur
17dcc120fb phy: lan966x: Extend lan966x to support multiple phy interfaces. 
Currently the driver is supporting only the interfaces QSGMII, SGMII,
RGMII and GMII. This patch extend the supported interfaces with
1000BASE-X and 2500BASE-X.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://lore.kernel.org/r/20211130101015.164916-1-horatiu.vultur@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-02 09:49:23 +05:30
Zou Wei
b2b56de9fa phy: intel: Remove redundant dev_err call in thunderbay_emmc_phy_probe() 
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1637822289-24534-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-12-02 09:46:33 +05:30
Fabrice Gasnier
77ba6e7ffb phy: stm32: adopt dev_err_probe for regulators 
Change stm32-usbphyc driver to use dev_err_probe(), to benefit of
devices_deferred debugfs in case of probe deferral.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/1635172265-26219-1-git-send-email-fabrice.gasnier@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-11-26 11:26:51 +05:30
Rafał Miłecki
97ba12d3fe phy: bcm-ns-usb2: improve printing ref clk errors 
Improve message & use dev_err_probe() helper which prints actual error
(helpful for debugging) and deals with -EPROBE_DEFER.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20211123221521.25323-1-zajec5@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-11-25 10:45:04 +05:30
Rashmi A
97004c1a4c phy: intel: Add Thunder Bay eMMC PHY support 
Add support of eMMC PHY for Intel Thunder Bay SoC,
uses the Arasan eMMC phy

Signed-off-by: Rashmi A <rashmi.a@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20211027115516.4475-5-rashmi.a@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-11-23 13:11:52 +05:30
Rashmi A
efb6935dd7 dt-bindings: phy: intel: Add Thunder Bay eMMC PHY bindings 
Binding description for Intel Thunder Bay eMMC PHY.
Added the newly introduced files into MAINTAINERS file-list

Signed-off-by: Rashmi A <rashmi.a@intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211027115516.4475-4-rashmi.a@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-11-23 13:11:52 +05:30
Horatiu Vultur
305524902a phy: Add lan966x ethernet serdes PHY driver 
Add the Microchip lan966x ethernet serdes PHY driver for interfaces
available in the lan966x SoC.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20211116100818.1615762-4-horatiu.vultur@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-11-23 13:09:08 +05:30
Horatiu Vultur
ea8a163e02 dt-bindings: phy: Add constants for lan966x serdes 
Lan966x has: 2 integrated PHYs, 3 SerDes and 2 RGMII interfaces. Which
requires to be muxed based on the HW representation.

So add constants for each interface to be able to distinguish them.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20211116100818.1615762-3-horatiu.vultur@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-11-23 13:09:08 +05:30