add a driver for the hardware watchdog timer embedded in NVIDIA
Tegra SoCs
Change-Id: I45bc829f26f350143d5a07e1f4ddc46d24f3a54c
Signed-off-by: Gary King <gking@nvidia.com>
update the suspend platform data for ventana to match recent changes
Change-Id: I142123027453ee34f80c094fb7cf1fcb464e889d
Signed-off-by: Gary King <gking@nvidia.com>
only reset the controller when doing so won't also reset the phy (Tegra quirk)
Change-Id: I549a18977d0d5ebfa12c32016aa9e6bffaa8643c
Signed-off-by: Gary King <gking@nvidia.com>
driver supports the MGG1010AI06 and EGG1010AI06 capacitive touch panels
Change-Id: I038030bf4c9acbd0d3d504427a32f4e46632c115
Signed-off-by: Gary King <gking@nvidia.com>
drivers/mmc/core/mmc.c:228: error: ‘SZ_256K’ undeclared (first use in this function)
Introduced by:
mmc: subtract boot sectors from disk size for eMMC 4.3+ devices
(SZ_* doesn't exist on anything but arm)
Change-Id: I981217adea4ef56bf870562b6711488f3f4bf830
Signed-off-by: Olof Johansson <olof@lixom.net>
initialize baud rate and configuration settings to safe default values
when receive DMA is in use, so that the DMA request may be enqueued at
initialization time
re-enqueue the receive DMA buffer immediately it is dequeued by the
DMA threshold callback and the receive ISR, rather than waiting for the
DMA complete callback
originally fixed by Gary King <gking@nvidia.com>
Fixing tx trigger level setting:
On tegra uart, the FCR setting for different tx trigger level
is not same as the 16550 tx trigger level setting. The tegra
uart have the setting in reverse direction on tx fifo attention
level:
b00 for 16 bytes attention level.
b01 for 8 byte attention level.
b10 for 4 byte attention level
b11 for 1 byte attention level.
The rx trigger attention level match with the standard uart
FCR register setttings.
Also fixing the typo in code when setting DTR.
originally fixed by Laxman Dewangan (ldewangan@nvidia.com)
Change-Id: Iea00478f143e61c604828035c6c92d614fa7cccb
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
tegra_start_tx was called directly by the serial core, as
well as from dma and serial interrupts to queue the next
block of data. Separate out the "queue next data"
functionality into tegra_start_next_tx.
Also fixes TX PIO by adjusting FIFO sizes and prevents
last characters from getting lost by spinning on TEMT
before disabling clocks.
Change-Id: If8ce15490f77dcbde48f1e64959d5c3f0ec35120
Signed-off-by: Colin Cross <ccross@android.com>
the csd sector count reported by eMMC 4.3+ cards includes the boot
partition size; subtract this from the size reported to the disk
since the boot partition is inaccessible
Change-Id: I601b83aa0159b7aa446409ea8c945b256dd0b5b1
Signed-off-by: Gary King <gking@nvidia.com>
0 is a valid GPIO number (GPIO_PA0), so the check in the tegra
SDHCI driver for a valid card detect pin should compare against -1
instead
Change-Id: I47ad31eaf89472b2e6938978d72a9d0b92a74958
Signed-off-by: Gary King <gking@nvidia.com>
Modern monitors/tvs have more extended EDID information blocks which can
contain extra detailed modes. This adds a fb_edid_add_monspecs function
which drivers can use to parse those additions blocks.
Signed-off-by: Erik Gilling <konkers@android.com>
The host (or host1x) bus sits between the cpu core and the 3d, 2d, camera,
display, and mpeg encoder functions. It contains provides DMA channels,
hardware mutexes, and synchronization points.
Signed-off-by: Erik Gilling <konkers@android.com>
-- Removed debugfs interface for toggling DMA
-- Added it under sysfs
-- Also added attributes for settings the attention levels of the i2s fifos
Signed-off-by: Iliyan Malchev <malchev@google.com>
This patch removes redundant i2s fifo resets, which also cause blips on playback.
It also moves the fifo attention levels to struct audio_stream.
Signed-off-by: Iliyan Malchev <malchev@google.com>
Add an ioctl to allow the TX fifo to be loaded with data before playback
starts. Playback can then be started by calling write() on the FIFO, even
with a length of 0. This will cause the pending data to be played out.
Signed-off-by: Iliyan Malchev <malchev@google.com>
-- Use consistently the various state flags:
-- active is set only when there is a read or write in flight
-- recording_canncelled is set only when recording is stopped via the ioctl()
-- dma_has_it is used to determine whether DMA is already in flight; do not
use the state of the fifos for this (e.g., if the TX fifo is empty, do not
assume that playback is stopped)
-- added a stop_completion (implemented for readers only) so that readers
closing a stream can wait until DMA or PIO transactions are stopped
-- Split /dev/audio0_{in,out} into /dev/audio0_{in,in_ctl,out,out_ctl} where the
_ctl versions have the ioctl()s
-- Introduced an error count per audio_stream; error count is reset on open, can
be read back & reset through an ioctl
Signed-off-by: Iliyan Malchev <malchev@google.com>
-- Add ioctls for configuring buffer, threshold, and DMA-transaction sizes from
user space.
-- Buffer sizes are provided in orders of magnitude.
-- Allocate max-sized buffers during probe, and allow the user to resize them
only within the original allocation, to avoid the risk from kmalloc failing
due to kernel-heap fragmentation, and also to avoid race conditions on DMA
shut-down.
-- In tegra_audio_write(), moved the call to start_playback_if_necessary()
immediately after writing to the fifo. Otherwise, when the fifo size is
smaller than what the user is trying to write, the user will block before
playback is started.
-- Silenced printk spew on spinning on i2s registers after transactions are
completed.
-- Cleaned up a 80-col style violation in downsample()
Signed-off-by: Iliyan Malchev <malchev@google.com>
On suspend, use phy_suspend save the phy registers so that there is
no need to reset the controller and re-enumerate devices on resume.
Change-Id: I00fe5b87a1b319044724494b8e635b540088a38b
Signed-off-by: Benoit Goby <benoit@android.com>
Reset the controller when the cable is unplugged to leave it in the idle
state. The OTG driver will reconfigure it on vbus/id pin detection.
Change-Id: I87903ec86f3c35af64a141f27a34cc0720a61b08
Signed-off-by: Benoit Goby <benoit@android.com>
phy_suspend save the phy registers and power it off. phy_clk_disable
disable the phy clock to put the phy in low power mode.
Change-Id: If5665ec96beec9441fae3b737923dbe69c86e650
Signed-off-by: Benoit Goby <benoit@android.com>
The OTG driver will power it up on ID pin detection. This avoids
race conditions when the device is powered on with the otg cable
attached.
Change-Id: I6bd5f1d73284f9b8534ef3dfb936b81a9400fa5b
Signed-off-by: Benoit Goby <benoit@android.com>
The clock to the ARM TWD local timer scales with the cpu
frequency. To allow the cpu frequency to change while
maintaining a constant TWD frequency, pick a lower target
frequency for the TWD and use the prescaler to divide down
to the closest lower frequency.
This patch provides a new initialization function that takes
a target TWD frequency and the relation between the cpu
clock and the TWD clock, required to be an integer divider
>= 2 by the ARM spec. It also provides a function to be
called from cpufreq drivers to set the prescaler whenever
the cpu frequency changes.
Also fixes a typo in the printk of the calibrated frequency.
Change-Id: I3fa8ef718ff5518170f1b2bab29efe960741853e
Signed-off-by: Colin Cross <ccross@google.com>
downsampling:
-- add ioctl()s to downsample recorded data
-- supported frequencies are 8kHz, 11.025kHz, 22.05kHz, and 44.1kHz
-- downsamping to stereo and mono
-- default is 11.025kHz mono
fixes:
-- fix crashes from dequeuing DMA requests twice
Signed-off-by: Iliyan Malchev <malchev@google.com>
On tegra, the UTMIP PAD control logic is common to all utmip phys and
are controlled from usb1. This adds a reference count to turn off the
pads when all utmip phy are off.
Change-Id: I3537d5cc52df929f817e547a79da235394d2c265
Signed-off-by: Benoit Goby <benoit@android.com>
-- add audio_in_stream (identical to audio_out_stream, may merge them later)
-- add support for DMA and PIO recording
-- add ioctls for /dev/audio<n>_in to start and stop recording
Signed-off-by: Iliyan Malchev <malchev@google.com>
