1.Delete the assigned-clock
2.Only rely on spi-max-frequency configuration in sub nodes
Change-Id: Ia8961e12ef5f6812ac12de1b6fdfdb5f6bda8267
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Some device DPCD Reversion is 1.2, but It can't write
Ainfo register REAUTHENTICATION_ENABLE_IRQ_HPD bit. For there
devices, it should avoid write REAUTHENTICATION_ENABLE_IRQ_HPD
bit.
It better to write REAUTHENTICATION_ENABLE_IRQ_HPD bit to Ainfo
register just when the DPCE Reversion higher than 1.2.
Change-Id: I10dcae33e8f33c9d41a05752caebc9cd085e729b
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
In DisplayPort HDCP1.3 Spec Section 2.2.2 page 12, It
indicate that the maximum-permitted time to receive ready
status bit is 5s for repeater.
Change-Id: I5a01c742328c2c6dfbd49fa31f952ab5b858fee0
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
In DisplayPort HDCP1.3 CTS case 1A-01 page 10, unencrypted video
signal should be sent before enable hdcp.
In DisplayPort HDCP2.2 CTS case 1A-1 page 12, unencrypted video
signal may be sent before enable hdcp.
Change-Id: I12f5ec4143728683663cba5a0f079c915c500383
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The benchmark test shows a significant score drop from 87038 to 73764,
if enabling UFSHCD_CAP_RPM_AUTOSUSPEND, due to the slow recover process
during readom rw test.
Meanwhile we finally have a power consumption result, which shows even more power
consumption was observed due to the phy/unipro status mismatch, one side is in H8,
another side lost the link.
|scene | UFS 128G rpm disable |UFS 128G rpm enable |
|-------------------------------------------------------------------------------------|
|screen 3.8V |TEMP25 |DDR |V |mA |VBAT |V |mA |VBAT |
|-------------------------------------------------------------------------------------|
|Static Desk |36 |528 |3.8V |419.11 |3.845|414.2 |3.8V |418.79 |3.843|414.1|
|-------------------------------------------------------------------------------------|
|Static Desk[1]|36 |528 |3.8V |125.76 |3.882|123.1 |3.8V |127.05 |3.881|124.4|
|-------------------------------------------------------------------------------------|
|1080P video |36 |528 |3.8V |556.83 |3.827|552.9 |3.8V |584.63 |3.829|580.2|
|-------------------------------------------------------------------------------------|
|1080P video[2]|36 |528 |3.8V |525.06 |3.837|520 |3.8V |499.98 |3.839|494.9|
|-------------------------------------------------------------------------------------|
|Note: [1] no screen [2] no buffering |
|-------------------------------------------------------------------------------------|
Moreover it significantly increases the possibility of failing to wait UIC ready state,
which can lead to very long reset and restore link process, adding more latency to the
system.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I9839fdb4a93c0ecae4b581f07db3281a40a2fa25
The PWM io input/output state is controlled by PWM mode
configuration. In order to avoid the antagonistic drive
state between the PWM pin and the external pin, keep the
PWM mode fixed in capture mode although PWM is disabled.
Change-Id: I6183987c9bef6f444726643f878c5384f63844d0
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:2386: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* rockchip_atomic_helper_update_plane copy from drm_atomic_helper_update_plane
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:2386: warning: missing initial short description on line:
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:2458: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* drm_atomic_helper_disable_plane copy from drm_atomic_helper_disable_plane
drivers/gpu/drm/rockchip/rockchip_drm_vop.c:2458: warning: missing initial short description on line:
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ie9d2e00238e4c45d6a8ad7581ea7482b14092a23
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:6139: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c:6210: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I24f65edf0c4900c09d5b68411a8f2dd473260ce6
The event of the notification does not match the actual status
Type: Fix
Redmine ID: N/A
Associated modifications: N/A
Test: N/A
Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ib2a9cb1888c27c74cc14f0f09707a670e65f0aa2
for hardware reason, we need judge wakeup sources to avoid wakeup
screen by wrong irq when wakeup from ultra sleep
Change-Id: I5a3ef85eb71a312ba0a9e992b70ef0b14e00fc47
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
spi_nor_write_sr will pollute the buffer of sr_cr buffer when calling
spi_nor_read_sr.
Change-Id: I217141297df4f448b64c61f1573e7e40d6874903
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
The crtc_clock div2 has been done at drm_mode_convert_to_origin_mode() from
the following commit:
commit 649255c0e3 ("drm/rockchip: drv: Add crtc_clock convert in
drm_mode_convert_to_{split,origin}_mode()")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I530d9582a52cea7d432208bc835fb19be051a7a0
The GMAC0/1 and MMU0/1(PCIe, SATA, USB OTG1) support CCI
(Cache Coherent Interconnect), Mark them as such.
Hardware feature for CCI were enabled at U-Boot miniloader level.
Note that MMU2 for USB OTG0 doesn't support CCI.
Change-Id: Ie632fc2ad987c3972076f65559c043b3da67d858
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to VESA DisplayPort Ver.1.4a - 5.1.1.1 Video
Colorimetry and CEA-861-F - 5.1 Default Encoding Parameters,
YCbCr format default use limit range. RGB format default
use limit range for CEA timing(except 640x480p or color depth
is 6 bit), and other timing should use full range.
The VOP Video Port only support full range when output RGB
format. So we just default config RGB format as full range
and YCbCr format as limit range.
Change-Id: I27e60c314c8cd17f69aa85eb380357fd8a78990f
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Fixes: 80647eb888 ("media: i2c: rk628: fix csc process mode and add range switch by user")
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I2ffd203fa69ce7d73a38f00be47ef3ee9a8fcd07
