The ROM code for Rockchip platform never support detecting
SD 3.0 mode, so if the SD card contains system image running
into SD 3.0 mode in kernel, it will fails to reboot.
The problem is SD 3.0 mode is using 1.8V signal and could only
be switched back into 2.0 mode by power cycle. If the customed
board could not switch off its power rail, the ROM code can't
soft reset the SD.
Add mmc_sd_shutdown to workaround this special case and don't
bother normal SD cards used as external disk by checking the
RESTRICT_CARD_TYPE_MMC flag.
Change-Id: I4c3d3111c0bce0ad3cd4f0c6592ff595d7015afe
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
If the device has a 'power-domains' property that the power framework
prefer to use dev_pm_ops for suspend&resume. The legacy suspend & resume
callback for nandc driver would not be used.
Anyway, it's better use dev_pm_ops whether 'power-domains' is existent.
Change-Id: I0e2822a44f3f0d458b778636cd84c5ae54505cf5
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
1.Filling the HDMI AVI infoframe quantization range information.
2.If output is limited enable color space conversion to convert.
Change-Id: I75f666424f00f3f6ec695047f7851824e89cd1a5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
New Inno combphy improve its pre-emphasis settings, so we
need to use new recommended value instead.
Change-Id: I5b4b2e8819c4b44d908156bb8ad99bd8c62c8bdf
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
modify head file to match the change of camera engine
Change-Id: Ia139e733f766cf9cbb02e80ceda81a1817b3acbf
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
According to the hardware test, change the tx pin drive strength
to 4ma, and mdc/mdio 2ma.
Change-Id: Ia5ab1728c9e9ecbfa7207217649588f600070ae4
Signed-off-by: David Wu <david.wu@rock-chips.com>
drivers/power/rk817_battery.c:3254:12: warning: 'rk817_bat_pm_resume' defined but not used [-Wunused-function]
error, forbidden warning:rk817_battery.c:3254
static int rk817_bat_pm_resume(struct device *dev)
^~~~~~~~~~~~~~~~~~~
drivers/power/rk817_battery.c:3037:13: warning: 'rk817_bat_pm_suspend' defined but not used [-Wunused-function]
error, forbidden warning:rk817_battery.c:3037
static int rk817_bat_pm_suspend(struct device *dev)
Change-Id: I8cb39c95688e16027257c09a20eaeb100bd1024b
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
we replace cru assigned clock node in rk1808-evb-x4 dts, and now clk_32k_ioe
is setted in this node, so we need to add this back in rk1808-evb-x4.dts,
otherwise the SOC can not boot normally.
Change-Id: I06a55bea97e0ef260f2549349b3211a311a913ae
Signed-off-by: Lin Huang <hl@rock-chips.com>
There was a typo when generating endpoint name which
would be very confusing when debugging. Fix it.
Change-Id: If29433f427499674b7604b399cbc3ac6e6bf7b1f
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit 696fe69d7e)
To support preisp post-processing and camera hal1,
let driver probe ok when no sensor device is connected.
Change-Id: I1830420f448b47a0bd327ee3950da0eb7af8d3fb
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
fix the following error on RK1808.
error: implicit declaration of function 'kzalloc' [-Werror=implicit-function-declaration]
inf = kzalloc(sizeof(*inf), GFP_KERNEL);
error: implicit declaration of function 'kfree' [-Werror=implicit-function-declaration]
kfree(inf);
Change-Id: Ie46828b03a45cc523b8503fb62caeccee165142f
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
The DWC3 rockchip driver provides a sysfs interface "dwc3_mode"
to force Peripheral mode or Host mode. It has a problem to force
to Host mode when the DWC3 works as Peripheral mode and connects
to Host (e.g. PC USB Port).
This issue can be reproduced on RK1808 EVB follow these steps:
1. Set dr_mode = "otg" in DTS dwc3 node;
2. Start the system, and connect the RK1808 USB 3.0 to PC USB.
3. Make sure that PC has recognized the USB device, and then
force DWC3 to Host mode via "dwc3_mode".
echo "host" > /sys/devices/platform/usb/dwc3_mode
And plug in an USB 2.0 Device to RK1808 USB 3.0 Port, then
we can see the following error log:
rockchip-dwc3 usb: Peripheral disconnect timeout
rockchip-dwc3 usb: USB unconnectedxhci-hcd
xhci-hcd.3.auto: xHCI Host Controller
xhci-hcd xhci-hcd.3.auto: new USB bus registered, assigned bus number 3
xhci-hcd xhci-hcd.3.auto: hcc params 0x0220fe64 hci version 0x110 quirks 0x04010010
...
hub 4-0:1.0: USB hub found
hub 4-0:1.0: 1 port detected
rockchip-dwc3 usb: USB HOST connected
rockchip-dwc3 usb: set new mode successfully
usb 3-1: new high-speed USB device number 2 using xhci-hcd
usb 3-1: new high-speed USB device number 3 using xhci-hcd
usb usb3-port1: attempt power cycle
usb 3-1: new full-speed USB device number 4 using xhci-hcd
usb 3-1: Device not responding to setup address
usb 3-1: Device not responding to setup address
usb 3-1: device not accepting address 4, error -71
It's because that in this test case, the dr_mode is original otg
mode, and the current code only call phy_set_mode() to disconnect
the peripheral from PC host if the dr_mode is peripheral mode.
This cause dwc3_rockchip_otg_extcon_evt_work() wait peripheral
disconnect timeout, and DWC3 fail to do runtime suspend and resume
to initialized the DWC3 core register again.
This patch call phy_set_mode() to disconnect the peripheral if
the current dr_mode is peripheral or otg when force to host mode.
Change-Id: I733d364046abcb616cf3d99ed57ab8604a87eef6
Signed-off-by: William Wu <william.wu@rock-chips.com>
In dwc3_rockchip_async_probe(), if it tries to get hcd in
peripheral only mode (dr_mode = "peripheral"), a NULL pointer
deference will happen. Because hcd only be allocated and
initialized in host mode or otg mode.
We can reproduce this issue when set dr_mode to peripheral
in DTS, like rk3399pro-npu.dtsi, and get the following panic
log on RK1808 EVB:
Unable to handle kernel NULL pointer dereference at virtual address 000000b0
pgd = ffffff8008b0b000
[000000b0] *pgd=000000007fffe003, *pud=000000007fffe003, *pmd=0000000000000000
Internal error: Oops: 96000005 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 29 Comm: kworker/u4:1 Not tainted 4.4.167 #493
Hardware name: Rockchip RK1808 EVB V10 Board (DT)
Workqueue: events_unbound async_run_entry_fn
task: ffffffc07cd29580 task.stack: ffffffc07cd40000
PC is at dwc3_rockchip_async_probe+0x28/0x1c8
LR is at async_run_entry_fn+0x48/0x100
pc : [<ffffff80083adf5c>] lr : [<ffffff80080b445c>] pstate: 60000045
sp : ffffffc07cd43d10
...
[<ffffff80083adf5c>] dwc3_rockchip_async_probe+0x28/0x1c8
[<ffffff80080b445c>] async_run_entry_fn+0x48/0x100
[<ffffff80080acca8>] process_one_work+0x1b8/0x2b8
[<ffffff80080ad94c>] worker_thread+0x304/0x418
[<ffffff80080b206c>] kthread+0xd0/0xd8
[<ffffff8008082e80>] ret_from_fork+0x10/0x50
Fixes: f2a2b34e45 ("usb: dwc3: rockchip: use async_schedule for initial dwc3")
Change-Id: I740936e43bc4ea2b5a056d6d9dcaf18466006f0c
Signed-off-by: William Wu <william.wu@rock-chips.com>
we use pdm mic as rk1808 evb board default mic array,
so enable pdm.
Change-Id: I45c4904fe865813185ab327da347d0b52418ef1c
Signed-off-by: Lin Huang <hl@rock-chips.com>
The only way of stopping the watchdog is by resetting it.
Add the watchdog op for stopping the device and reset if
a reset line is provided.
At same time WDOG_HW_RUNNING should be remove from dw_wdt_start.
As commented by Guenter Roeck:
dw_wdt sets WDOG_HW_RUNNING in its open function. Result is
that the kref_get() in watchdog_open() won't be executed. But then
kref_put() in close will be called since the watchdog now does stop.
This causes the imbalance.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: Wim Van Sebroeck <wim@iguana.be>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: linux-watchdog@vger.kernel.org
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
(cherry picked from commit 1bfe888938)
Conflicts:
drivers/watchdog/dw_wdt.c
Change-Id: Ia6f4e16011b61f78c09b5c54669ddd18678357b9
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
The dw_wdt has an external reset line, that can keep the device in reset
and therefore rendering it useless and also is the only way of stopping
the watchdog once it was started.
Get the reset lines for this core from the devicetree. As these lines are
optional, use devm_reset_control_get_optional_shared. If the reset line
is not specified in the devicetree, the reset framework will just skip
deasserting and continue.
This way all users of the driver will continue to function without
any harm, even if the reset line is not specified in the devicetree.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: linux-watchdog@vger.kernel.org
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
(cherry picked from commit 65a3b6935d)
Conflicts:
drivers/watchdog/dw_wdt.c
Change-Id: Iffbc95931869a5d595a348b6c08ee7da5a1e64e4
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Parse boot mode on system bootup, and export it to
userspace by sysfs: sys/kernel/boot_mode
Change-Id: I0158fc28f4dae51c798806006e49cead4ce2e923
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Coverity reports:
divide_by_zero: In expression readl(dw_wdt->regs + 8) /
clk_get_rate(dw_wdt->clk), division by expression clk_get_rate(dw_wdt->clk)
which may be zero has undefined behavior.
The clock used for the watchdog timer won't change its rate, so read it
only once during probe. Also validate it and abort the probe function
with an error if it is 0.
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
(cherry picked from commit c97344f73f)
Conflicts:
drivers/watchdog/dw_wdt.c
[due to missing:
f29a72c24a "watchdog: dw_wdt: Convert to use watchdog infrastructure"
and local version of:
3024e0d13b "watchdog: dw_wdt: fix signedness bug in dw_wdt_top_in_seconds()"]
Change-Id: Iea745e27224532bf4da560e5952b372289d1c6ae
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
RK3399 has rst_pulse_length in CONTROL_REG[4:2], determining the length
of pulse to issue for system reset. We shouldn't clobber this value,
because that might make the system reset ineffective. On RK3399, we're
seeing that a value of 000b (meaning 2 cycles) yields an unreliable
(partial?) reset, and so we only fully reset after the watchdog fires a
second time. If we retain the system default (010b, or 8 clock cycles),
then the watchdog reset is much more reliable.
Read-modify-write retains the system value and improves reset
reliability.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
(am from https://patchwork.kernel.org/patch/10273163/)
Conflicts:
core watchdog frameworks were reworked, so this moved from an
open() function to a start() function
BUG=b:74204857
TEST=force watchdog event before/after suspend/resume on kevin and scarlet;
check timing
Reviewed-on: https://chromium-review.googlesource.com/958088
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Change-Id: I18d5ec3604a44a671ba79ceea1821e733bf051fe
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
