We cache the invalid cached phase when the clock provider be
reparented from orphan to its real parent in the first place,
thus we may mess up the initialization of MMC cards since we
only set the default sample phase and drive phase later on.
So we should skip to restore the invalid phase.
Change-Id: I2d995a4ab53b824737718482f35fcaaf84767dfb
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
It's found that the clock phase output from clk_summary is
wrong compared to the actual phase reading from the register.
cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample
sdio_sample 0 1 0 50000000 0 -22
It exposes an issue that clk core, clk_core_get_phase, always
returns the cached core->phase which should be either updated
by calling clk_set_phase or directly from the first place the
clk was registered.
When registering the clk, the core->phase getting from ->get_phase()
may return negative value indicating error. This is quite common
since the clk's phase may be highly related to its parent chain,
but it was temporarily orphan when registered, since its parent
chains hadn't be ready at that time, so the clk drivers decide to
return error in this case. However, if no clk_set_phase is called or
maybe the ->set_phase() isn't even implemented, the core->phase would
never be updated. This is wrong, and we should try to update it when
all its parent chains are settled down, like the way of updating clock
rate for that. But it's not deserved to complicate the code now and
just update it anyway when calling clk_core_get_phase, which would be
much simple and enough.
Change-Id: I21e8899f4dc6cb0d244ea8c9741337b17da3308d
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
commit 1f9c63e8de)
vccio_sd and vcc_sd are well better controlled by MMC core
and please don't bother taking care of them instead, otherwise
reboot w/ a working SD3.0 card will fail to respond the correct
OCR in the first place as missing a proper power removal.
Change-Id: I9efa11e25198b66e21538bd6603a3bab6638dc5f
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
set frame effect to fix mistake fild when in interlace mode
Change-Id: I74143cc28cbd9a7864a1df57979f3888137c141c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
when video width is bigger than 3840 the linebuffer mode
should be LB_YUV_3840X5.
Change-Id: I27dce8a6fcb7f6f5b8d196671a515c68f188c101
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
On 32bit platform, vco may be out of range. The variable type
of vco needs to be set to u64.
Change-Id: I2f6b967278986bb77bf74c7a11794fc4d73645db
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
panel init cmds is not only for dsi panel, some mcu screen and
spi screen also need init cmds, so we update this panel init cmd
name and reuse this part logic.
Change-Id: I9e633647fa3f3d92eb90b443a8a5da99a24a3b42
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Gpu 480M is from usb480m and the source clocks should be always on
if change gpu frequency after power off pd.
Change-Id: I11b5b05381e1745919b7137a64e4d334786cf433
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
If the PWM pinctrl uses default state, the iomux setting will
be done at probe, the PWM may not be enabled at this moment.
It will make PWM into an intermediate state, destroy the default
hardware state, the PWM is not ready for work yet. So it is better
for doing PWM pinctrl setting after PWM enabled.
Change-Id: Iea34a7baf6a4d7df0c631f7f4fdab5b9d61bbd5f
Signed-off-by: David Wu <david.wu@rock-chips.com>
To slove the display shaking, when uboot logo display to kernel show.
Change-Id: Ifc97f72df27b4e8dbcd34ab8ed65ac027fd424d1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
For some reason drm driver maybe probe failed, so the drm_dev is
null. this will lead to kernel panic when enter suspend function.
Change-Id: Ic529ba9103d27b0766189285bd6cf8e43b23b912
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The controller will reset and run into error state if turn
off power when suspend in host mode. This patch stop hcd to
make the controller into L3 state to make sure that the
controller and driver state will reset when resume.
Change-Id: If66bc1a249e919f440ecde0c66f18dabde0b2e62
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The IR-Drop is always different between different boards, so we
need know the IR-Drop to adjust opp-table to guarantee stably
for the board.
Change-Id: I8ad05d30e15a7e62910a952cc6fa199d70129660
Signed-off-by: Liang Chen <cl@rock-chips.com>
1. Optimize the garbage processing.
2. Add data list for block manager.
Change-Id: I1c5563151e80dd3b3e941835dd93e2fe4eb4e20b
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>
On some chip, HDMI post PLL is not stable when it's vco is 1080M,
but it work ok when vco is 270M. We use a efuse bit to distinguish
these chip.
Change-Id: I143363d67e60747ee52d405edace3ec611de3e6e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
LEDS_IS31FL32XX is a led driver IC used by rk3308 evb.
Change-Id: I77c8dcd379e72bd85bffcad5f0ec51bbaf876274
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Inno hdmi phy post pll is enabled by default on rk3228, it's need to
manual power down post pll if uboot logo is not shown.
Change-Id: I7ed4de2eae2d723f390dae44281281b9e81f4e1d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
There are many factors affecting the clock phase, including clock
rate, temperature, logic voltage and silicon process, etc. But clock
rate is the most significant one here, and the driver should be aware
of the change of the clock rate. As mmc controller need a fixed phase
after tuning was completed, at least before explicitly doing re-tune,
so this patch try to restore the clock phase by monitoring the event
of rate change.
Change-Id: Id1ccdfd2e8d4e2eb9f6a1923b3813138dbaf99f7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from https://patchwork.kernel.org/patch/10269525/)
