Commit Graph

607090 Commits

Author SHA1 Message Date
Wen Nuan
ad46e68846 phy: rockchip: mipi-dphy-tx1rx1: add mipi-dphy TX1RX1 channel for RK3288
This patch adds the function of mipi-dphy TX1RX1 for RK3288, the
mipi-dphy TX1RX1 is matched when "txrx_base_addr" is valid.

Change-Id: I01640925157a7082e942188b29f6bbf1318cf3d5
Signed-off-by: Wen Nuan <leo.wen@rock-chips.com>
2018-02-13 09:39:36 +08:00
William Wu
67217a757a arm64: dts: rockchip: use spdifm2_tx for rk3328-evb-android
Change-Id: I6d13fb703deffccb87bc311733afb88c1c90bbdd
Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-02-11 21:13:25 +08:00
Sugar Zhang
84c9e0030a arm64: configs: rockchip_defconfig: enable pdm interface
Change-Id: I3d6b75d3e08bf542e8b0da014fd4a6b263fac124
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-02-11 21:08:29 +08:00
Sugar Zhang
8b8065853a arm64: dts: rockchip: px30: fixup pdm pinctrl
Change-Id: I5a3978a486c63dae718b46be142eed263788e5f3
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2018-02-11 21:08:17 +08:00
Tao Huang
2e98315186 arm64: rockchip_defconfig: enable CONFIG_CRYPTO_CRC32_ARM64
Change-Id: I70e8ba303d5c3b0210912a31e3175425c1f1a63f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 20:56:13 +08:00
Tao Huang
d1c247b600 sound/soc/codecs/rt5651: fix compile warning
sound/soc/codecs/rt5651.c:351:14: warning: duplicate const
declaration specifier [-Wduplicate-decl-specifier]

Change-Id: I25ac1012398c7742c7b66d6a57f4956b96ba0aa4
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 20:29:43 +08:00
Tao Huang
f1da8a190e sound/soc/codecs/rk817_codec: fix compile warning
sound/soc/codecs/rk817_codec.c:405:14: warning: duplicate const
declaration specifier [-Wduplicate-decl-specifier]

Change-Id: I572b1778f29a48b0756ac60488ce2311cc372f8b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 20:20:51 +08:00
Tao Huang
75df0e02ac ARM: rockchip_defconfig: bump CONFIG_ANDROID_VERSION to 0x08000000
Change-Id: Ia66100f8d828aa0ae3a7c3c66906c51d07548b92
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 19:23:00 +08:00
Tao Huang
4f33232979 Revert "Revert "ARM: rockchip_defconfig: enable CONFIG_IKCONFIG""
This reverts commit cbd1d90f72.

8588d88f1a ("ANDROID: android-base.cfg: add CONFIG_IKCONFIG option")

This adds CONFIG_IKCONFIG and CONFIG_IKCONFIG_PROC options, which are a
requirement for the O release.

Change-Id: I438ade881219034618afb4cd5174bf750a79d319
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 19:22:54 +08:00
Tao Huang
badf2c4918 arm64: rockchip_defconfig: bump CONFIG_ANDROID_VERSION to 0x08000000
Change-Id: Iafd493187f579ec4f5d202a496548f70be7a868a
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 19:22:26 +08:00
Tao Huang
ea18c3d20d Revert "Revert "arm64: rockchip_defconfig: enable CONFIG_IKCONFIG""
This reverts commit 95bc3a8935.

8588d88f1a ("ANDROID: android-base.cfg: add CONFIG_IKCONFIG option")

This adds CONFIG_IKCONFIG and CONFIG_IKCONFIG_PROC options, which are a
requirement for the O release.

Change-Id: Id02fde91ed902f266ff5c81ec04e2427a2877847
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 19:22:10 +08:00
Tao Huang
aa349fbf38 ARM: rockchip_defconfig: remove CONFIG_ANDROID_LOW_MEMORY_KILLER
e8f5f841b764 ("remove CONFIG_ANDROID_LOW_MEMORY_KILLER requirement")

Kernel configuration options should include either
CONFIG_ANDROID_LOW_MEMORY_KILLER for in-kernel lowmemorykiller driver
to be used or a combination of CONFIG_MEMCG and CONFIG_MEMCG_SWAP
if userspace lmkd is preferred. It is not currently possible to express
this logical requirement in the config fragment so the
CONFIG_ANDROID_LOW_MEMORY_KILLER requirement is simply
removed for now.

Change-Id: I9cea0552a285ac635fc44f4b45762988e423d7db
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 19:21:55 +08:00
Tao Huang
7adc50bef2 arm64: rockchip_defconfig: remove CONFIG_ANDROID_LOW_MEMORY_KILLER
e8f5f841b764 ("remove CONFIG_ANDROID_LOW_MEMORY_KILLER requirement")

Kernel configuration options should include either
CONFIG_ANDROID_LOW_MEMORY_KILLER for in-kernel lowmemorykiller driver
to be used or a combination of CONFIG_MEMCG and CONFIG_MEMCG_SWAP
if userspace lmkd is preferred. It is not currently possible to express
this logical requirement in the config fragment so the
CONFIG_ANDROID_LOW_MEMORY_KILLER requirement is simply
removed for now.

Change-Id: I69b9682029a50f4579f3ba11e6a9a497c5a51c28
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 19:21:41 +08:00
Tao Huang
1dd2b51cdf net/wireless/rockchip_wlan: fix compile warning
Change-Id: Ife9d64914e2986a07a649064ee0141d83fea69e2
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-11 19:21:16 +08:00
Zorro Liu
d55db1d3ba arm64: dts: rockchip: modify gsensor layout value of px30-evb-ddr3-v10 board
Change-Id: I7ecdf9db002e3754189e345e27efbb249146539b
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
2018-02-11 19:18:00 +08:00
Zorro Liu
5db5490025 drivers: input: sensors: update accel sensor mma7660 driver
Change-Id: Id3cf0cf3a14a07010524d0de58dc523bfcb3b735
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
2018-02-11 19:17:53 +08:00
Caesar Wang
2a8ce270ad arm64: dts: rockchip: remove the hdmi-cec pinctrl for rk3399 excavator
As the edp_hpd pinctrl is reused by hdmi-cec. So the rk3399 will hit the
pinctrl register failed on bootup.

Says: the failed log:
[0.927577] rockchip-pinctrl pinctrl: pin gpio4-23 already requested by
ff940000.hdmi; cannot claim for ff970000.edp
[0.928519 ] rockchip-pinctrl pinctrl: pin-151 (ff970000.edp) status -22
[0.929112] rockchip-pinctrl pinctrl: could not request pin 151
(gpio4-23) from group edp-hpd  on device rockchip-pinctr

That will cause the edp can't work on rk3399 SoCs.

Fixes: commit
6e4eaff822 ("arm64: dts: rockchip: add HDMI cec support for rk3399")

Change-Id: I8ba20db55025e33c082beda5160e0398f1681766
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2018-02-11 19:17:18 +08:00
Finley Xiao
093bfc848c clk: rockchip: rk3328: Fix clk_cif_src parent
Change-Id: I0ea209224880b8c51a385ed46827bb0d8f7dd219
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-11 19:15:16 +08:00
Finley Xiao
0cb664eb76 clk: rockchip: px30: Remove clk_gpu_divnp5
Change-Id: I67f47f5fdd7873c22b1349e3aeb80b7157c7844c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-11 19:12:19 +08:00
Finley Xiao
f457f16cd2 clk: rockchip: px30: Fix clk_gmac_rmii_sel parent
Change-Id: Idf1bd416a3879048afd3763d4a6d056c34171bbb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-11 19:10:15 +08:00
Sandy Huang
ce0ec8d27b drm/rockchip: vop: alpha_pre_mul mode depend on user space
Change-Id: Iaada438902ddddbbd00890c53a58cc49af3c3d3e
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-02-11 19:08:48 +08:00
Sandy Huang
424a08f4cb drm/rockchip: px30 vop: delete win2
Change-Id: If36214c7f57c96d7a06e81db383300cff0669681
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2018-02-11 14:58:38 +08:00
Finley Xiao
aed92d3f61 clk: rockchip: px30: Fix clk_i2s0_rx parent
Change-Id: Ia523234cf5b210bbfe51cbf075943e7f44123ca9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-11 12:08:25 +08:00
Zheng Yang
5f1c036a65 drm/bridge: synopsys: dw-hdmi: fix kernel logo flash when output YCbCr422 mode
On rockchip platform, hdmi input format is YCbCr444 when output mode
is YCbCr422. Then the value of HDMI_TX_INVID0 on YCbCr422 is same as
the value of YCbCr444, both is 0x09/0x0b. This make enc_out_bus_format
stroed in struct hdmi_data is wrong, which is MEDIA_BUS_FMT_YUV8_1X24
or MEDIA_BUS_FMT_YUV10_1X30.

When android set enc_out_bus_format to YCbCr422, dw_hdmi_setup will be
called and logo will flash.

This patch use colorspace restored in HDMI_FC_AVICONF0 to distinguish them.

Change-Id: I6b913951b58fb47628617c11d6059bc1be4e370a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
2018-02-11 10:21:53 +08:00
Zhong Yichong
80f0ef45db arm64: dts: rockchip: rk3326 evb: enable isp
Change-Id: I0a41db448bbb51afcaa4b538cf0aefac25e7c762
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10 16:30:53 +08:00
Zhong Yichong
0bef3afae9 camera: rockchip: camsys_drv: disable cru reset of rk3326 isp now
Because it will cause CPU hangs on, so disable the reset temporarily.

Change-Id: I612be4b47145fd1ebf8d8e5d44270f26151768fa
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10 16:29:56 +08:00
Zhong Yichong
f943a72c35 arm64: dts: rockchip: px30: modify isp mipiphy count from 0 to 1
Change-Id: I878c8b6ee15885662c215b52143cd73474dd8cbf
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10 16:07:29 +08:00
Zhong Yichong
16bb8bd923 arm64: dts: rockchip: px30: modify the isp reg range
Change-Id: I3326908e0445c1230b73169b9d9b34a31658d0b2
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
2018-02-10 16:07:19 +08:00
shengfei Xu
69441faf9e mfd: rk808: rk809 chip name register is same as rk817
Change-Id: I22f5735ab3272a53d2e97012f452c340f16b0bff
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
2018-02-10 14:58:46 +08:00
Rocky Hao
9b2724a451 thermal: rockchip: fix channal invertion issue for px30
Change-Id: Ifed5628c18cece0658754095e718da39ac703413
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
2018-02-10 11:34:03 +08:00
Tao Huang
9b3f148373 ARM: rockchip_defconfig: enable CONFIG_MEMORY_STATE_TIME
f3d9c312b8 ("Implement memory_state_time, used by qcom,cpubw")

New driver memory_state_time tracks time spent in different DDR
frequency and bandwidth states.

Memory drivers such as qcom,cpubw can post updated state to the driver
after registering a callback. Processed by a workqueue

Bandwidth buckets are read in from device tree in the relevant qualcomm
section, can be defined in any quantity and spacing.

The data is exposed at /sys/kernel/memory_state_time, able to be read by
the Android framework.

Functionality is behind a config option CONFIG_MEMORY_STATE_TIME

Change-Id: Ic3b0b631efd697713360f193ede440cd9ad3bc29
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-10 10:34:38 +08:00
Tao Huang
319ff3657f arm64: rockchip_defconfig: enable CONFIG_MEMORY_STATE_TIME
f3d9c312b8 ("Implement memory_state_time, used by qcom,cpubw")

New driver memory_state_time tracks time spent in different DDR
frequency and bandwidth states.

Memory drivers such as qcom,cpubw can post updated state to the driver
after registering a callback. Processed by a workqueue

Bandwidth buckets are read in from device tree in the relevant qualcomm
section, can be defined in any quantity and spacing.

The data is exposed at /sys/kernel/memory_state_time, able to be read by
the Android framework.

Functionality is behind a config option CONFIG_MEMORY_STATE_TIME

Change-Id: I4391cc3ed42c9f332bce4a7809c6f120e2798dae
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-10 10:34:23 +08:00
Finley Xiao
884b0673a7 clk: rockchip: rk3288: Add TSP clock
Change-Id: I02185c5ab7a1072d271cd51161f6d4b05d327673
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-10 09:04:17 +08:00
Finley Xiao
a250f09aff clk: rockchip: rk3128: Add sclk_hsadc_tsp
Change-Id: I842869a7ea79730daa6616f1cf2a8f5db7165ceb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2018-02-10 09:04:17 +08:00
William Wu
33e05f0c21 CHROMIUM: phy: rockchip-typec: enable usb3 host after pipe ready
If we power off the SoC LOGIC rail in S3, we can find that the
Type-C PHY can't initialize correctly after system resume with
error log looked like this:
  phy phy-ff800000.phy.9: phy poweron failed --> -110
  dwc3 fe900000.dwc3: failed to initialize core
  dwc3: probe of fe900000.dwc3 failed with error -110

It's because that the field of usb3tousb2 in GRF_USB3PHY0/1_CON0
is reset to 1 after power off the SoC LOGIC, which means that the
pipe interface is blocked between Tpye-C PHY and usb3 controller.
And after system resume, the rockchip_usb3_phy_power_on() will call
the tcphy_cfg_usb3_to_usb2_only() to clear the usb3tousb2 bit and
enable the usb3 host again. If we clear the usb3tousb2 bit before
pipe ready, it may cause waiting for pipe ready timeout.

Note that the RK3399 TRM suggests that we should keep the whole usb3
controller in reset for the duration of the Type-C PHY initialization.
However, it's hard to assert the reset in the current framework of
reset. And according to the TRM, it doesn't require that we should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.

BUG=b:62644399, chromium:783464
TEST=run suspend_stess_test on Scarlet, usb device can work after resume

Change-Id: Ie597cbe35568c390460aa2fdbad0e66c6104c8d2
Reviewed-on: https://chromium-review.googlesource.com/896908
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
2018-02-10 09:03:29 +08:00
William Wu
fd186f221b CHROMIUM: usb: dwc3: rockchip: reset host controller at resume
If we power off the SoC LOGIC rail in S3, it seems that the host
controller comes back in an undefined state, such that the Type C PHY
can't initialize correctly. We need to toggle the USB3-OTG reset before
trying to initialize the PHY, or else it often times out.

Note that the TRM suggests we should be asserting this reset for the
duration of the PHY initialization, but we're still skeptical about
that, and we haven't yet found a case where this seems to have mattered.
Besides, this approach is much easier.

The dwc3 core is going to reinitialize the controller at suspend/resume
anyway (including a "soft reset"), so it should be safe to do this,
regardless of whether the system actually powered off the USB logic.

For hygiene's sake, it's good to wait some small bit of time in between
asserting/de-asserting this reset. Might as well apply this to both
instances of this reset.

BUG=b:62644399
TEST=suspend/resume scarlet with LOGIC disabled in S3; USB comes back OK
     also test suspend/resume on kevin for USB regressions

Change-Id: I5b5354d0fb9c7ed9d2c9044ddfbb5f7709884fb7
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/877404
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2018-02-10 09:03:29 +08:00
David Wu
f8c5fa1e6b arm64: dts: rockchip: increase the i2c1 scl frequecny to 400k for rk3326-evb-lp3-v10
Base on the rise time of scl test, the scl frequecny could be
increased to 400k.

Change-Id: I17f858b28ed11992411c52e5f83424b0187d097c
Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-10 09:02:25 +08:00
David Wu
99079676c2 arm64: dts: rockchip: increase the i2c0 scl frequecny to 400k for rk3326-evb-lp3-v10
Base on the rise time of scl test, the scl frequecny could be
increased to 400k.

Change-Id: I9af57e13a97f0866ec4f0dd295f9bcf4cbeee304
Signed-off-by: David Wu <david.wu@rock-chips.com>
2018-02-10 09:02:07 +08:00
Huibin Hong
68b095de9e spi: rockchip: add compatible rockchip,px30-spi for px30
Change-Id: Ibe406477b3912b482d07e5c0e7f8e2e99a51bd4a
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09 18:57:11 +08:00
Huibin Hong
02dcfc3420 arm64: dts: rockchip: add uart aliases, modify uart1 clk for px30
Change-Id: Ia1accabbb76c1f1e4deb11aae055bec328ec5a61
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09 17:57:09 +08:00
Huibin Hong
d51654309d spi: rockchip: test: remove unused code
Change-Id: I7b44f7c3a8e32eaf2c550d915c45a3394816c925
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09 17:56:22 +08:00
Tao Huang
4b4a117433 ARM: rockchip_defconfig: enable CONFIG_AIO
4ed084e489fd ("Move CONFIG_AIO to android-base.")

CONFIG_AIO has legitimate use for the functionfs
driver, which is used with adb and mtp. It is now
required to be enabled for better performance
with those services.

Change-Id: I52d05c734a25b35e012666b010b2ee5426915094
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 17:54:35 +08:00
Tao Huang
6f04df2fa9 arm64: rockchip_defconfig: enable CONFIG_AIO
4ed084e489fd ("Move CONFIG_AIO to android-base.")

CONFIG_AIO has legitimate use for the functionfs
driver, which is used with adb and mtp. It is now
required to be enabled for better performance
with those services.

Change-Id: I631fac8e56ea16711f0cc05297140dc59c9fb581
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 17:54:25 +08:00
Huibin Hong
6716ded459 arm64: dts: rockchip: add spi1 cs1 for px30
Change-Id: I933b76ed4b312a713e390c130ef6b5c090e3779c
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2018-02-09 17:49:42 +08:00
Tao Huang
e868d4ecb9 ARM: rockchip_defconfig: remove CONFIG_PM_AUTOSLEEP
6e30a9a158bd ("remove CONFIG_PM_AUTOSLEEP from android-base.cfg")

Autosleep is no longer used by Android.

Change-Id: Ia024dbb6343abd8e1016febc08251dc5dc7badc1
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 17:33:47 +08:00
Tao Huang
3c4e6c9040 arm64: rockchip_defconfig: remove CONFIG_PM_AUTOSLEEP
6e30a9a158bd ("remove CONFIG_PM_AUTOSLEEP from android-base.cfg")

Autosleep is no longer used by Android.

Change-Id: I7ff5c40a8cdfbe9e67019bc859eb940fae2b6c4f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2018-02-09 17:33:40 +08:00
Algea Cao
0b86943d0e mfd: rk1000: Support rk1000 uboot logo
Reading rk1000's register to see whether uboot logo was on.

Change-Id: Iee6d15213f16ccd59136a5cf4f4017f5cd40ab62
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-02-09 16:44:58 +08:00
Algea Cao
4262e671f9 arm64: dts: rk3368-r88: support rk3368 drm cvbs uboot logo
Removing ports so that uboot display subsystem can get
rk1000 as panel.

Change-Id: If12c30bb7d1bd382ed969534687234aa79b8dd04
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-02-09 16:44:41 +08:00
Algea Cao
bcc83cb2ff drm/bridge: Support rk1000 kernel logo
Setting connector port to support kernel logo

Change-Id: I594eec0a924ecf1c47c82d61c471dd21c2af1830
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
2018-02-09 16:44:17 +08:00
shengfei Xu
569bb500f8 arm64: dts: rockchip: rk3326: use extcon specifier for the charger
Change-Id: Ie84c6be541c6489ca93cef38f5ad3741851fdb59
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
2018-02-09 16:40:07 +08:00