support delay time in microseconds required to
rise or fall to this new voltage
Change-Id: I1f7c77356e650b9ff01ad0e63fd384e25f774eac
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The meaning of the property value is as below:
The value of the property EXTCON_PROP_USB_SS is 0: USB1.0 or USB2.0
The value of the property EXTCON_PROP_USB_SS is 1: USB3.0
we change the logic of fusb302 notification , if dp sink device is connected, dfp is set to 1,
and use pin assignment value to define if sink device support usb3.0.
Change-Id: Ib7afaf9b754b4585b0ef211dd246059b8ab72904
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
The disvr usb audio sampling rate is through nanoc reported to
the kernel, so don't need the kernel again set the sampling rate.
Change-Id: I60409fc579952a196c4fe40f678e87d505a7508d
Signed-off-by: wjh <wjh@rock-chips.com>
No need notify charging-external-connector state when otg host connect.
Change-Id: I1d5c6e4fb2ad504f169ef0fd5b82b06f31783922
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Some rk3399 board(rk3399 MID or rk3399 VR) is use rk81x generated vbus.
So need fusb302 send a extcon to notify rk818 when OTG or DP cable plugin.
If use EXTCON_USB_HOST, the extcon will notify dwc3 and rk818_charger at
the same time,so need to add a new extcon EXTCON_USB_VBUS_EN.
Change-Id: Ib019ed7c2d4343c50dcef739ab3076f592979ea0
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
No functional change. Rename "enum phy_mode" to
"enum xgene_phy_mode" in xgene phy driver in
preparation for adding set_mode callback in
phy core.
Change-Id: I7e569e1fb82a308e79d30a80323e0c3c338dd68c
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Loc Ho <lho@apm.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 65048f4dd9)
rk3399-box Type-C0 USB needs to support peripheral mode
and host mode, so we set dr_mode as otg.
Change-Id: If94cdca3ec1d018c3f9aad14bb2c1e15e10e9c51
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The upstream commit 5e8ec28765 (usb: dwc3: gadget: Handle TRB
index 0 when full or empty) only use the HWO = 1 to check if
the TRB ring is full. But refer to DWC3 databook Version 3.00a,
8.2.3.2 TRB Control Bit Rules: When an OUT endpoint receives a
short packet, some TRBs in a chain may still have their HWO bit
set to 1 while belonging to software.
So if HWO=1 and CSP=1 on OUT endpoint, it also means that TRB
ring is empty, software may reclaim those TRBs even though HWO=1.
TEST=use MTP to transfer big data, and then cancel the transition，
check if it can transfer again.
Change-Id: I45cc683dc733ff7a642cfcd3ebc20455ef677753
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The initial use for this is for PHYs that have a mode related to USB OTG.
There are several SoCs (e.g. TI OMAP and DA8xx) that have a mode setting
in the USB PHY to override OTG VBUS and ID signals.
Of course, the enum can be expaned in the future to include modes for
other types of PHYs as well.
Change-Id: Iebc730d7e41c2910fa1be98cbf275d2c73358050
Suggested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 300eb0139c)
Add the new extcon EXTCON_USB_VBUS_EN to enable
vbus output.
Change-Id: I83fb75b2a82ad617dc292967bb4917bbfbcb84cb
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Fix commit 536277d550 ("FROMLIST: extcon: Add the support for
extcon property according to extcon type"), which introduce
EXTCON_PROP_USB_ID property, but upstream don't have such property.
Remove it make merge easy.
Change-Id: I7905049629aa85158b7e705b40018f83fa85a9ac
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
HCI_UART_PROTO_SET flag is set before hci_uart_set_proto call. If we
receive data from tty layer during this procedure, proto pointer may
not be assigned yet, leading to null pointer dereference in rx method
hci_uart_tty_receive.
This patch fixes this issue by introducing HCI_UART_PROTO_READY flag in
order to avoid any proto operation before proto opening and assignment.
Signed-off-by: Loic Poulain <loic.poulain@intel.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
Change-Id: Ibe366f3222cbe7a093cd08aaecbc0de1004088c8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 84cb3df02a)
If enable cabc function, close auto gating, because cabc and auto gating
can't enable at the same time, in addition cabc open and close will lead
to splash screen, so when close cabc, we just set stage up and down to 0.
Change-Id: Ia4561d6adafa956c26d1921caecc7eed97dd218a
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
As we register regmap irq to manage rk818 irqs, it should
not enable/disable irq by modifying register directly. And
check otg on/off line state before setting new state.
Change-Id: I45d45d62bea05b1c489337ac7f3334fbafcd4166
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>
This is a workaround for the issue that
"400M, 500M and 600M of clk_gpu needs high vdd_gpu",
according to "6.1" of Mali Application Note
"Potential glitches on Power Domain interfaces".
Change-Id: I58daa3cf796802f073f67bacb62734516be76205
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
if the dclk_vop0_div allow CLK_SET_RATE_PARENT for VPLL,
the dclk_vop1_div parent is not allowed in vpll.
Change-Id: I9973014e8ed2fcf1c351e3f62c00040677391ff7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The uart may be reinitialized when resume, if uart is in busy
state, which would fail to configure the baud rate. So reset
and set uart to loopback mode can make sure uart is in idle
state.
Change-Id: I54d9ac8de1531cd06da8c223583cd2e330178eff
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
When the pointer of hcd is NULL, dwc3 driver will probe again. In this
case the notify sync function will issue "Bad mode in Synchronous Abort
handler detected" error if the extcon notify is not unregisted before
next probe. This patch add unregister extcon notify function and
unregister extcon notify when hcd is NULL.
Change-Id: Id55ce4280518e0c7e36a64133e38189bb4a7d29e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
If the adc drift value is 70, some keys maybe report twice, because
the range of adc_value +/-70 is overlapping other keys' adc range.
So it is better configuring adc drift value from DT, that also can
support more keys at a adc channel. The default adc drift value is
70, if it does not get the drift value from DT.
Change-Id: I46cef235094116d4f03af5e5c0cd3a6dfe7e8b0d
Signed-off-by: David Wu <david.wu@rock-chips.com>
In the case of platform designed in usb2.0 only mode, which
the dwc3 controller connect without fusb302 and type-c phy
does not work, the u2phy need to support hot plug and detect
otg mode, this patch add support of otg function in this mode.
Change-Id: I428a4f6d17d847c6114d124733e62c0a6236b94e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The probe function of usb controller will remove hcd struct in host
or otg mode, while the hcd is alloced after xhci driver registed. So
there is a logical error if xhci driver is registed after usb
controller and it results in the pointer of hcd point to NULL. This
patch make usb controller probe again if hcd point to NULL.
Change-Id: I659f86decac59fca610b355356fc971b3a86d4be
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
used unsigned int pointer that regmap_read wanted instead of unsigned char
pointer
Change-Id: I89f838144a4d27a3bf695232acc4dbbe920863bf
Signed-off-by: zain wang <wzz@rock-chips.com>
Per the vendor's requirement, we shouldn't do any setting for
1.8V Signaling Enable, otherwise the interaction/behaviour between
phy and controller will be undefined. Mostly it works fine if we do
that, but we still see failures. Anyway, let's fix it to meet the
vendor's requirement. The error log looks like:
[ 93.405085] mmc1: unexpected status 0x800900 after switch
[ 93.408474] mmc1: switch to bus width 1 failed
[ 93.408482] mmc1: mmc_select_hs200 failed, error -110
[ 93.408492] mmc1: error -110 during resume (card was removed?)
[ 93.408705] PM: resume of devices complete after 213.453 msecs
Change-Id: Icc5457355c3f57b84bd6073f0c4e01350bcc9ee6
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
Per JESD84-B51 P69, Host need to change frequency to <=52MHz after
setting HS_TIMING to 0x1, and host may changes frequency to <= 200MHz
after setting HS_TIMING to 0x3. It seems there is no difference if
we don't change frequency to <= 52MHz as f_init is already less than
52MHz. But actually it does make difference. When doing compatibility
test we see failures for some eMMC devices without changing the
frequency to hs_max_dtr. And let's read the spec again, we could see
that "Host may changes frequency to 200MHz" implies that it's not
mandatory. But the "Host need to change frequency to <= 52MHz" implies
that we should do this.
Change-Id: I1dc9f5fa8dc217e033fc4b1689ca1b0204c294c0
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
When introducing hs400es, I didn't notice that we haven't
switched voltage to 1V2 or 1V8 for it. That happens to work
as the first controller claiming to support hs400es, arasan(5.1),
which is designed to only support 1V8. So the voltage is fixed to 1V8.
But it actually is wrong, and will not fit for other host controllers.
Let's fix it.
Change-Id: I982bf34b3d305123ab7debd858e60f2454123c24
Fixes: commit 81ac2af657 ("mmc: core: implement enhanced strobe support")
Cc: <stable@vger.kernel.org> 4.4# +
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
Per spec, block size should always be 512 bytes for dual rate mode,
so any attempts to switch the block size under dual rate mode should
be neglected.
Change-Id: I6ede0d8fd6c7b8e4903a51c1c2a1b96d350bd2e2
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>
