Since evb2 couple with ES1, the power consumption is large enough to
shutdown device in some case.
Let's reduce it's support lists to make things simple.
Change-Id: I145aa0c6a21e41b3c8e6ff32fd15839baa15f81e
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Let's disable it as the auto link training of PCIe
take quite long time without add-in card or M.2
devices available.
Change-Id: I4a48a44574b68da75845a6e614a9970bb5d6685b
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Fix them for matching what the new drivers want.
Change-Id: I6ce43379ab9cf3d274b6b414ec014e431db588b7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Add support for the Rockchip PCIe controller found on RK3399 SoC platform.
Change-Id: Ic924a0defaef195575beba4dfc92c33b6b5bc3e7
[Shawn: manually backport to 4.4 with some minor changes]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Several host bridge drivers iterate through the list of bridge windows to
request resources. Several others don't request the window resources at
all.
Add a devm_request_pci_bus_resources() interface to make it easier for
drivers to request all the window resources. Export to GPL modules (from
Arnd Bergmann <arnd@arndb.de>).
Change-Id: I4b89f0739d66d6027bfd2a01e9e93f5218ade617
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 950334bcf1)
This patch to add a generic PHY driver for rockchip PCIe PHY.
Access the PHY via registers provided by GRF (general register
files) module.
Change-Id: Ieba96d9cdf0d96302f38d29789615e2ec93f3440
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
These must be translated from the values in the TRM by subtracting 32,
which has not been done.
Change-Id: I8d26bd63d39009b60b310e7ccbcd5de814863861
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
When connected with type-c to standard-a cable, inno phy will
generate an interrupt before setting the state of typec to host,
which result in detecting of battery charger. This patch change
the state to host before interrupt happen.
Change-Id: I6a2e15c264bd6729c3b8d23af23ad15145559b20
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Add a binding that describes the Rockchip PCIe controller found on Rockchip
SoCs PCIe interface.
Change-Id: Ifb84320315c06759612f2b3d9b2b6ff3e1e5cb1e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
This patch adds a binding that describes the Rockchip PCIe PHY found
on Rockchip SoCs PCIe interface.
Change-Id: I18940e940e0c951d3e2d6bb3b2131a37727a430d
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
If pwm polarity was configured with different values at uboot,
the enable_conf would not be configured correctly.
Change-Id: I55b9ccc262382951a8a82810f1be74ce9460f266
Signed-off-by: Zhou weixin <zwx@rock-chips.com>
1. modify clock-names, according to Heiko's suggestion, clock names
should always be in the scope of the device block (named after what
it supplies), and clock-names are always meant from the perspective
of the individual ip-block.
2. remove unnecessary clocks, refer to rk3399 TRM, aclk_usb3 is the
parent of aclk_usb3otg0/1 and aclk_usb3_grf, and we will enable
aclk_usb3otg0/1 and aclk_usb3_grf, so don't need to enable aclk_usb3
again. In addition, the aclk_usb3_rksoc_axi_perf clk is used for usb3
performance monitor module which we don't use now, so don't need to
enable it.
Change-Id: I1d50a72d1523b8b70f1e5f388dc357807131dd7c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
When do Rx compliance test, PHY is in loopback mode, we
observed that Rx test failed with long cable, and it was
found that equalizer adaptation is not happening properly.
With rx_eq_training forced from PMA, the equalizer adaptation
working fine and Rx test can pass. The root cause is that
the Rx REE component will be turned off when control data
is being received by default PHY configuration. So we need
to unmask REE control data by setting REE control data mask
register, and with this patch, equalizer training will happen
based on the signal coming from controller only.
Change-Id: Ic4fca1045d92381470588c4afccff0cc7318ab4c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
userspace will set several frame after vop suspend, so the kernel back
buffer will be freed and after resume vop will read a freed buffer and lead
to post empty, so we close all win before suspend, after resume vop will
display black until userspace set a new frame.
Change-Id: I6648861d2162f221e7fbf85d2361ad245e7b88aa
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
Since edp screen couple with another type of touchscreen,
so disable gt9xx to reduce i2c errors.
Change-Id: I829ae12039ecaea44c4e0734c18a5ebcd41845f8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This patch remove emmc node for rk3288-miniarm board.
because the new version of the hardware does not use emmc.
Change-Id: I72914a4e570342e5b0b559b3400e0a9db8aea7eb
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
regmap_write
->_regmap_raw_write
-->regcache_write first and than use map->bus->write to write i2c or spi
But if the i2c or spi transfer failed, But the cache is updated, So if I use
regmap_read will get the cache data which is not the real register value.
Change-Id: Iae06edf8a2a50d2561d351a8398bd3140904630c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git
commit 815806e39b)
there define two devfreq_event_get_drvdata() function in devfreq-event.h
when disable CONFIG_PM_DEVFREQ_EVENT, it will lead to build fail. So
remove devfreq_event_get_drvdata() function.
Change-Id: I273e91d4aac48ae25af5ef6de2feb37944cf6e39
Signed-off-by: Lin Huang <hl@rock-chips.com>
add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.
Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4
Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Lin Huang <hl@rock-chips.com>
According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.
Change-Id: I49540085036982e6c496a3b911805f0b67fa79e1
Signed-off-by: John Youn <johnyoun@synopsys.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit b8ccc593ee)
Calls to dwc2_core_reset() are currently very slow, taking at least
150ms (possibly more). It behooves us to take as many of these calls
out as possible.
It turns out that the calls in dwc2_fs_phy_init() and dwc2_hs_phy_init()
should (as documented in the code) only be needed if we need to do a PHY
SELECT. That means that if we see that we can avoid the PHY SELECT then
we can avoid the reset.
This patch appears to successfully bypass two resets (one per USB
device) on rk3288-based ARM Chromebooks.
Change-Id: If9f7275d61af6fd8558124ff9ebc7c3622c1f4a3
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 7d56cc2620)
I found that the probe function of dwc2 driver takes much time
when kernel boot up. There are many long delays in the probe
function these take almost 1 second.
This patch trying to reduce unnecessary delay time.
In dwc2_core_reset() I see it use two at least 20ms delays to
wait AHB idle and core soft reset, but dwc2 data book said that
dwc2 core soft reset and AHB idle just need a few clocks (I think
it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
board), so 20ms is too long, delay 1us for wait AHB idle and soft
reset is enough.
And in dwc2_get_hwparams() it takes 150ms to wait ForceHostMode
and ForceDeviceMode valid but in data book it said software must
wait at least 25ms before the change to take effect, so I reduce
this time to 25ms~50ms. By the way, is there any state bit show
that the force mode take effect ? Could we poll curmod bit for
figuring out if the change take effect ?
It seems that usleep_range() at boot time will pick the longest
value in the range. In dwc2_core_reset() there is a very long
delay takes 200ms, and this function run twice when probe, could
any one tell me is this delay time resonable ?
I have tried this patch in my RK3288-evb board. It works well.
Change-Id: I1f42ab6b6851f0721bf93d516bee895ebcdd994f
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 20bde64343)
