Commit a44f7cb937 ("mmc: core: use mrq->sbc when sending CMD23 for
RPMB") began to use ACMD23 for RPMB if the host supports ACMD23. In
RPMB ACM23 case, we need to set bit 31 to CMD23 argument, otherwise
RPMB write operation will return general fail.
However, no matter V4 is enabled or not, the dwcmshc's ARGUMENT2
register is 32-bit block count register which doesn't support stuff
bits of CMD23 argument. So let's handle this specific ACMD23 case.
From another side, this patch also prepare for future v4 enabling
for dwcmshc, because from the 4.10 spec, the ARGUMENT2 register is
redefined as 32bit block count which doesn't support stuff bits of
CMD23 argument.
Fixes: a44f7cb937 ("mmc: core: use mrq->sbc when sending CMD23 for RPMB")
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20201229161625.38255233@xhacker.debian
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ic31c6f626b869620a2656cb84ecb01fe03700a4e
(cherry picked from commit ca1219c0a7)
Allow SDHCI drivers to hook code before and after sdhci_request() by
making it externally visible.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I3e144e8f597d49479fbed8528519c257f740d3f2
(cherry picked from commit d462c1b474)
Select ION_CMA_HEAP to support cma memory allocated from ion driver.
Change-Id: I9bb44004e8e86e00795f85c31946eb8bb3f12006
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The ion allocates memory defaultly with memset to zero, userspace should
do cache sync before read/wirte after map.
But the userspace always not to do that.
This patch supports to do force sync for memory allocated first time
from page pools with memset zero.
Change-Id: I8a65b1a3259d315459a0489f9c51ab0855957a70
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
when vp0 and vp1 indenpendent config layer_sel register, this register take effect
time is prone to error, so we add the following measures to workaround this issue:
1. Add commit_lock to make sure vp0 and vp1 config register is mutually exclusive;
2. Make sure layer sel register is take effect when it's update.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ief832e2bf7e18567f4ea663843c77f0afbd21cf7
the fs raw bit will be cleared by vop2_isr() fs irq and lead to
vop2_wait_for_fs_by_raw_status() time out, so we use
vop2_wait_for_fs_by_done_bit_status() to wait done bit from 1 to 0 is
more reliable.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ice35fb9bfe6c2ef7a49496b15b9f58bf93e95d4e
We thought when userspace switch hdmi to hdr mode, it must
give vop a hdr plane, but We meet a case: composer give
vop only one sdr plane, but switch hdmi to hdr mode.
so we don't check the plane number for sdr2hdr_en;
Change-Id: I4804a88321af84328735d6499ac9df610bf2cb85
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
1. limit vmin of cpu/gpu/npu/logic by mbist_vmin.
2. raise vdd_logic when npu run at 1.0GHz or venc run at 400MHz.
3. disable npu@1.0GHz and venc@400MHz by default.
4. reduce vdd_logic for the chips with big leakage.
5. adjust low-temp-adjust-volt table.
Change-Id: If7ce6f010422d20e2dfd643a6894fa7304e6372f
Signed-off-by: Liang Chen <cl@rock-chips.com>
Add support for rk3568 and init opp-table with rockchip_init_opp_table()
so that rockchip_bus can support pvtm and leakage.
Change-Id: Ief17dba8264906f987d4dac93b2e7344c98bc8fa
Signed-off-by: Liang Chen <cl@rock-chips.com>
1. support get pvtm from otp.
2. adjust opp-table by mbist_vmit which is get from otp.
Change-Id: Ie3703873880b65b2af03ae474065d541c7f9d605
Signed-off-by: Liang Chen <cl@rock-chips.com>
Fixes: b25c12a00a ("scripts: add io-domain.sh for rk356x io-domain check")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I5b8d8706b48f32a6ba2dbeebabf3a5bd2ba24678
In preparation to enable building SCMI as a single module, let us move
the SCMI protocol registration call into the driver. This enables us
to also add unregistration of the SCMI protocols.
The main reason for this is to keep it simple instead of maintaining
it as separate modules and dealing with all possible initcall races
and deferred probe handling. We can move it as separate modules if
needed in future.
Link: https://lore.kernel.org/r/20200907195046.56615-4-sudeep.holla@arm.com
Tested-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
(cherry picked from commit 1eaf18e35a)
Conflicts:
drivers/firmware/arm_scmi/reset.c
drivers/firmware/arm_scmi/system.c
Change-Id: Iec1dbc42c49367a1fa7299cb359f1214021ada6b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
In preparation to enable building scmi as a single module, let us move
the scmi bus {de-,}initialisation call into the driver.
The main reason for this is to keep it simple instead of maintaining
it as separate modules and dealing with all possible initcall races
and deferred probe handling. We can move it as separate modules if
needed in future.
Link: https://lore.kernel.org/r/20200907195046.56615-3-sudeep.holla@arm.com
Change-Id: I6f1a6ce7cc4c2b6f281add5f5d6a7ca3cbad9eca
Tested-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit 5a2f0a0bdf)
RK3568 u2phy used shared interrupt and do not used id irq.
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: I341cc0edb0f74996f159c095545465673cc2a990
1. pmuio1 on RK3568 SoC supports 3.3v only, no register to set.
2. vccio2 used for flash, which select by hardware
Change-Id: Ie168626906b52dea5b789b6b4dfcf1e45eb5f08a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Before the change: The sizeof rk3568_pll_rates = 2544
Use union: The sizeof rk3568_pll_rates = 1696
In future Soc, more PLL types will be added, and the
rockchip_pll_rate_table will add more members,
and the space savings will be even more pronounced
by using union.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 23029150a0
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git v5.14-clk/next)
Change-Id: Ia8f038861c327feb41602cc9a997e82333fae67b
Fixes: b25c12a00a ("scripts: add io-domain.sh for rk356x io-domain check")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I7e1c657102fd782a359c3aabfbbdbdf63875f675
The squashfs multi CPU decompressor makes use of get_cpu_ptr() to
acquire a pointer to per-CPU data. get_cpu_ptr() implicitly disables
preemption which serializes the access to the per-CPU data.
But decompression can take quite some time depending on the size. The
observed preempt disabled times in real world scenarios went up to 32ms,
causing massive wakeup latencies. This happens on all CPUs as the
decompression is fully parallelized.
So replace CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU by CONFIG_SQUASHFS_DECOMP_MULTI.
Change-Id: I3fb74bca595ee2345f2f7c276eaf8cc68bcd249b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
fix cts CaptureRequestTest#testEdgeModeControl[1] &
CaptureRequestTest#testNoiseReductionModeControl[1] failed
failed log:
Frame duration must be in the range of [33333333, 66666666],
value 32813000 is out of range [32833332, 67666664])
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Icdc6a89f33d6d0fd8332c51033afe6303e246ce3
when open video0/1/2/3 first, then close it;
if reopen video0, the output data is green;
if not enable iommu, it's ok; fix it;
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Ib977c34f005548bbc21cc93ca39c10d871235ad9
Algos private data should store in tfm's ctx field to avoid
modify by other algos while calculating.
Change-Id: I1c77e408e3374c697849ec508323131bf5f488b2
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Rename some struct name and variable name been more clearly.
Change-Id: Icf5e6f9d1a7e3f4abfbe05b3fb0034651a120039
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
To fix problem in redmine #297983, make some rules about fiq_target_cpu:
The default value of fiq_target_cpu is zero and
can only be updated in sip_fiq_debugger_switch_cpu
or sip_fiq_debugger_enable_fiq.
View redmine#297983 for details.
Change-Id: I947a73c3ffc0c818a611e108a343f05b8465645b
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
When using 24MHz reference clock, some devices can't identify
the SATA PM chip, And the signal quality is not as good as 100MHz.
so change the reference clock to 100MHz.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If7d951a0b77d503f9faf1c1f88c78a9e07471e47
EPD_A2 mode use part update to save panel power cost
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I65181c3ef51034b9302532f9f1276ebd2724d0ee
usage:
csi has 4 available channels, generally id0->vc0, id1->vc1, id2->vc2, id3->vc3.
A channel can only takes one data type. When you need to collect spd data or embedded data,
you can use an idle channel and change its vc to be consistent with active data.
dts configuration:
imx258: imx258@10 {
rockchip,spd-id = <3>;//use id3 to capture spd data
rockchip,ebd-id = <2>;//use id2 to capture embedded data
};
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I89a0f9472bbe475c9da368b09eaad0cd00fc69c6
