AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | AFBC_FORMAT_MOD_YTR |
AFBC_FORMAT_MOD_SPARSE | AFBC_FORMAT_MOD_SPLIT defined
twice.
This may cause weston startup failed at:
weston: ../libweston/drm-formats.c:451: weston_drm_format_add_modifier:
Assertion `!weston_drm_format_has_modifier(format, modifier)' failed.
Change-Id: I5e1a1832e3a5d939487023d3a0a7eb3f984468ea
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The rk730 codec driver is mainly used for the rk3506g-demo-display-control board.
Change-Id: I40a9c162bf1c8d9bfc6a2163fda38bb4e2049716
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This version has made a lot of updates to the rk730 codec driver.
Including:
- Fixed dapm routing path and definition description
- The capturing and playbacking functions work normally
- Corrected the final description of registers according to the manual
Aims to make the rk730 codec driver more convenient and easy to use
on general platforms.
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: Ia9fb477681433dc5ec5e2ca8c6b526a9dc1d5cb2
The register scl_lb_mode is only used at rk3528 platform,
the cluster lb is self assigned by IC designed.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia54648adeda9b7262fa56fbd37c7310e1bce8ff1
only vdpu382 use mmu reset as ip soft reset
Change-Id: I9e1dd2b9a0d5e9c29afa9f1c9392e8e12cea8d2e
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
If don't clear write/read bits when ddc
transmission fails, ddc transmission may
always fail no matter how many times retry.
Change-Id: I8f1a64432a1fb2afffc9404dcfb911f01f8188ad
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Fixes: dd812e1c19 ("media: i2c: rk628: set CPLL_REF_CLK to 1194M")
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: Ib406041a530cea8e86cee36deff267e2ec02719d
Rockchip platform actually doesn't support prefetchable, make pcie0
and pcie0 consistent with each other.
This also remove the invalid type warning from Firmware when using
kernel DTB.
=> pci e
pci_uclass_pre_probe, bus=0/pcie@2a200000, parent=root_driver
decode_regions: len=28, cells_per_record=7
decode_regions: region 0, pci_addr=20000000, addr=20000000, size=100000, space_code=0
decode_regions: region 0, pci_addr=20100000, addr=20100000, size=100000, space_code=1
- type=1, pos=0
decode_regions: region 1, pci_addr=20200000, addr=20200000, size=e00000, space_code=2
- type=0, pos=1
decode_regions: region 2, pci_addr=900000000, addr=900000000, size=80000000, space_code=3
- type=8, pos=2
pcie@2a200000: PCIe Linking... LTSSM is 0x0
pcie@2a200000: PCIe Linking... LTSSM is 0x0
pcie@2a200000: PCIe Link up, LTSSM is 0x130011
pcie@2a200000: PCIE-0: Link up (Gen2-x1, Bus0)
pcie@2a200000: invalid flags type
Change-Id: I24ed9d105d68d05508697e5db54b3f3909520adc
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Use user-defined mcu bypass timing if mcu-bypass-timing
node has been found in dts, otherwise setup the default
timing which can meet the read/write timing requirements
of most mcu panel.
Change-Id: I1225eed1e9dbca5adafd2d674bc9b6c709b2b1dd
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The reading function can be used for debugging while trying
to bring up the mcu panel, or reading some specific status
regs during the frame blanking period, and etc.
Change-Id: I29b153a78aa4a0ebb64f3156a37fddc67986bb49
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
For RK3506 and later platforms, it is recommended to sync
mcu bypass timing with dclk rather than hclk on earlier
platforms as IC design. And different platform has its
own recommended mcu bypass timing to meet the needs of
most mcu panels.
Change-Id: I9ce07e63dc7d2a717dbbb31ed13c98b41f25edc8
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
