IP cores whose clock is under aclk_vdpu_low_pre should not be changed
after power on. If one reduce frequence of clock, others will be
affected and will take longer time to finished work.
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
Change-Id: I631dd9a3f47c5811d6ae27f558a25a98d6022f49
1.Support get_dma_status for polling DMA status
2.Remove the struct of dw_pcie from dmatest
Change-Id: Ifef2b9172234e597354d9ae410d3f39be55cc6a8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Rootcause:
Those devices that do not have multicores but share one mpp_taskqueue,
due to the core_id is default value 0, will fail to attach workqueue.
Thus making mpp->queue = NULL and will crash when use mpp->queue.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I805aeadce1ec47ba18f2410864b83dca947655db
At the beginning, we skip walking the PCIe bus if the root port is
in L0 to save the suspend time. However, when enabling L1ss, the
threshold from L0 to L1ss is quite longer than from L0 to L0s or L1.
So we may in the middle stage that PCIe link hasn't wait long enough
to do transition from L0 to L1ss, at that moment we may still in L0.
rk_pcie_downstream_dev_to_d0 won't be called in this situation and
we miss all the ASPM settings. Ideally, we should walk the bus and
decide if anyone of them was marked as ASPM enabled in advanced, then
record ASPM settings. But in this way, there is no difference by fixing
it just as leting remove link state judgement.
Fixes: 0a082fd9da ("PCI: rockchip: dw: Save&Restore L1SS in PM")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ic0cdf74271241dc78cfd5d23c6c027e82f35bde2
If current task finish with soft timeout, the next
task in pending list will not get processing.
So, need to trigger again in mpp_task_timeout_work to
ensure that next task in pending task gets processed in time.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Iefa57c883eda81553c1b4c17be4f18c4dc83c946
Based on hardware testing, the change could improve the rising
edge and falling edge for RXCLK.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6779f2c1bcdf0e3b9aaa1553e4456cd581304302
Based on hardware testing, the change could improve signal quality for RGMII.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibba6130308f152922848687bb00c04a41efce5bc
Enable the following macros for AMP system:
CONFIG_ROCKCHIP_AMP=y
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ie8335e429d0da4414994df553351611351c24704
Workaround for FIFO clear on SLAVE mode:
A Suggest to do reset hclk domain and then do mclk
domain, especially for SLAVE mode without CLK in.
at last, recovery regmap config.
B Suggest to switch to MASTER, and then do FIFO clr,
at last, bring back to SLAVE.
Now we choose plan B here.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iac775ff092c6d16e0240459e60fc8112b54f61c6
1. Modify the polarity configuration.
2. Monitor timing changes using VMON_VMEAS/VMON_HMEAS interrupts.
3. Add sip_hdmirx_config operation, cooperate with bl31 reset
controller logic.
4. Configure the HPD low time to 1 second to enhance compatibility.
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I4f55e0ece74df7c9e82391bae6afb4154fec96d9
The otg wakelock should be destroyed when the device probe failed
or removed, else may cause the following kernel errors.
list_add corruption. next->prev should be prev (ffffffc01209d3c8), but
was 0000000000000000. (next=ffffff800350faf8).
------------[ cut here ]------------
kernel BUG at lib/list_debug.c:25!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
Modules linked in:
CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.10.110 #83
Hardware name: Rockchip RK3562 EVB1 LP4X V10 Board (DT)
pstate: 60400085 (nZCv daIf +PAN -UAO -TCO BTYPE=--)
pc : __list_add_valid+0x6c/0x88
lr : __list_add_valid+0x6c/0x88
[...]
Call trace:
__list_add_valid+0x7c/0x98
wakeup_source_register+0x120/0x160
wakeup_source_register+0x120/0x160
device_init_wakeup+0x60/0xf4
[...]
So add devm action to fix it.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: If54a299a694414ad759002e4f6c4187448ccdb15
1.ensure hardware is being off status when task done
2.add soft reset process for iep
3.enable hw timeout
4.disable md_pre when md_lambda == 8
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I700fffddc9a7a2c37b9790d938a243978fa3abdc
"cpu_online_mask" hasn't been cleared yet in CPUHP_AP_ONLINE_DYN stage.
So we use cpumask_any_but instead of cpumask_first.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I0a29d18869f50ac584fc545d27045f631045d568
add rkvdec link info for vdpu382 version
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I7ec36faf021de723257595f0df99cce4722442a0
Try to get the maximum PD revision which Type-C controller can
support from DT, and use this value to init the PD negotiated
revision instead of hard coded values 0x0300 (PD3.0).
This can fix at least the following two Type-C controllers issues:
1. FUSB302 failed to response PD Message "Get Source Cap Ext" if
used the default negotiated revision PD_MAX_REV (PD_REV30)
with MacBook (test on macOS 12.2.1).
2. ET7301B failed to detect the voltage status of the measured
CC pin for vRd-3.0 if used the default negotiated revision
PD_MAX_REV (PD_REV30) with some Type-C DP monitors.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I2c9bcc06ff2b3d678a6eab5013cec7f45cbda3dd
This property is used to tell the maximum USB Power Delivery
revision which Type C controller can support.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ibc0b35096ae270cd6d0e67cbdb2e5b85604f43b3
