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Krzysztof Kozlowski
d24539a6a9 arm64: dts: qcom: sm8250: drop incorrect Coresight funnel properties 
There is only one output port, thus out-ports should not have
'address/size-cells' and unit addresses.  'reg-names' are also not
allowed by bindings.

  qrb5165-rb5.dtb: funnel@6042000: out-ports: '#address-cells', '#size-cells', 'port@0' do not match any of the regexes: 'pinctrl-[0-9]+'
  qrb5165-rb5.dtb: funnel@6b04000: Unevaluated properties are not allowed ('reg-names' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-2-krzysztof.kozlowski@linaro.org
 2023-03-15 15:42:02 -07:00
Krzysztof Kozlowski
d882778eb4 arm64: dts: qcom: drop incorrect cell-index from SPMI 
The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index'
property:

  sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-1-krzysztof.kozlowski@linaro.org
 2023-03-15 15:41:53 -07:00
Bartosz Golaszewski
9ebaa4a8cd arm64: dts: qcom: sm8150: fix the uart9 label 
There's a typo in the @<address> part of the uart9 label. Fix it.

Fixes: 10d900a834 ("arm64: dts: sm8150: add the QUPv3 high-speed UART node")
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230315202751.1518543-1-brgl@bgdev.pl
 2023-03-15 15:31:46 -07:00
Manivannan Sadhasivam
65d9975e5d arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

On SM6350, there is only one LLCC bank available. So let's just pass that
as "llcc0_base".

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-12-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:22 -07:00
Manivannan Sadhasivam
413c8ecd48 arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-11-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:22 -07:00
Manivannan Sadhasivam
7ae317cba6 arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-10-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:22 -07:00
Manivannan Sadhasivam
42c9b15782 arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-9-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
c5ccf8d33f arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-8-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
0fe0955a79 arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-7-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
62e5ee9db9 arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

While at it, let's also fix the size of the llcc_broadcast_base to cover
the whole region.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-6-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
116a932bbc arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

On SC7180, there is only one LLCC bank available. So let's just pass that
as "llcc0_base".

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-5-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Manivannan Sadhasivam
bfe088bde3 arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks 
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as
there are LLCC BWMON registers located after this range.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-4-manivannan.sadhasivam@linaro.org
 2023-03-15 15:17:21 -07:00
Konrad Dybcio
d0af0537e2 arm64: dts: qcom: msm8996: Add missing DWC3 quirks 
Add missing dwc3 quirks from msm-3.18. Unfortunately, none of them
make `dwc3-qcom 6af8800.usb: HS-PHY not in L2` go away.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230302011849.1873056-1-konrad.dybcio@linaro.org
 2023-03-14 19:30:48 -07:00
Mukesh Ojha
d39469f5ce arm64: dts: qcom: sm8450: Add IMEM and PIL info region 
Add a simple-mfd representing IMEM on SM8450 and define the PIL
relocation info region, so that post mortem tools will be able
to locate the loaded remoteprocs.

Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1677079845-17650-1-git-send-email-quic_mojha@quicinc.com
 2023-03-14 19:30:48 -07:00
Bartosz Golaszewski
5d793ff406 arm64: dts: qcom: sa8775p: add cpufreq node 
Add a node for the cpufreq engine and specify the frequency domains for
all CPUs.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230221150543.283487-3-brgl@bgdev.pl
 2023-03-14 19:30:48 -07:00
Krzysztof Kozlowski
aec576821e arm64: dts: qcom: apq8096-db820c: fix indentation 
Correct indentation.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230220094339.47370-2-krzysztof.kozlowski@linaro.org
 2023-03-14 19:30:48 -07:00
Krzysztof Kozlowski
5a1816cc2d arm64: dts: qcom: msm8996: move WCD9335 audio codec to boards 
The WCD9335 audio codec on Slimbus is a property of a board, not SoC,
thus it should not be present in MSM8996 DTSI.  Keep it in specific
boards, so it won't appear incomplete in the boards not having it.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230220094339.47370-1-krzysztof.kozlowski@linaro.org
 2023-03-14 19:30:47 -07:00
Konrad Dybcio
78c61b6b2c arm64: dts: qcom: sm8350: Add qcom,smmu-500 to Adreno SMMU 
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-5-konrad.dybcio@linaro.org
 2023-03-14 19:30:47 -07:00
Konrad Dybcio
8347b12e90 arm64: dts: qcom: sm8250: Add qcom,smmu-500 to Adreno SMMU 
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-4-konrad.dybcio@linaro.org
 2023-03-14 19:30:47 -07:00
Konrad Dybcio
3e5c002568 arm64: dts: qcom: sm8150: Add qcom,smmu-500 to Adreno SMMU 
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-3-konrad.dybcio@linaro.org
 2023-03-14 19:30:47 -07:00
Konrad Dybcio
c564b69984 arm64: dts: qcom: sc7280: Add qcom,smmu-500 to Adreno SMMU 
Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230216145646.4095336-2-konrad.dybcio@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
0e6538e2d9 arm64: dts: qcom: sm6115: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-13-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
d9ab57eec3 arm64: dts: qcom: sm6375: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-12-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
2051f735b3 arm64: dts: qcom: sc8280xp: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-11-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
c2a18730f0 arm64: dts: qcom: sm8350: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-10-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
fc7258948c arm64: dts: qcom: sm8150: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-9-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
7b39c98ff7 arm64: dts: qcom: sc7180: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-8-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
fcca74d893 arm64: dts: qcom: qdu1000: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-7-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
d78cb07dbc arm64: dts: qcom: sm8250: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-6-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
1b0911fe3e arm64: dts: qcom: sm8550: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-5-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
afa34380d9 arm64: dts: qcom: sm6350: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-4-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
667d8a2039 arm64: dts: qcom: sc7280: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-3-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:47 -07:00
Manivannan Sadhasivam
2af2ef08c0 arm64: dts: qcom: sdm845: Supply clock from cpufreq node to CPUs 
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-2-manivannan.sadhasivam@linaro.org
 2023-03-14 19:30:46 -07:00
Bartosz Golaszewski
603f96d4c9 arm64: dts: qcom: add initial support for qcom sa8775p-ride 
This adds basic support for the Qualcomm sa8775p platform and the
reference board: sa8775p-ride. The dt files describe the basics of the
SoC and enable booting to shell.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230214092713.211054-3-brgl@bgdev.pl
 2023-03-14 19:30:46 -07:00
Konrad Dybcio
0d589dc92f arm64: dts: qcom: pm8998: Add a specific compatible for coincell chg 
Add a PM8998-specific compatible to the coincell charger and keep the
PM8941 one as fallback.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230214090849.2186370-3-konrad.dybcio@linaro.org
 2023-03-14 19:30:46 -07:00
Konrad Dybcio
b5d08f0837 arm64: dts: qcom: msm8998: Fix stm-stimulus-base reg name 
The name stm-data-base comes from ancient (msm-3.10 or older)
downstream kernels. Upstream uses stm-stimulus-base instead. Fix it.

Fixes: 783abfa224 ("arm64: dts: qcom: msm8998: Add Coresight support")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230213210331.2106877-1-konrad.dybcio@linaro.org
 2023-03-14 19:30:46 -07:00
Konrad Dybcio
5a0c6d4349 arm64: dts: qcom: sm6375: Add RMTFS 
Add a node for RMTFS on SM6375.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230213175928.1979637-1-konrad.dybcio@linaro.org
 2023-03-14 19:30:46 -07:00
Krzysztof Kozlowski
d228efe884 arm64: dts: qcom: sm8550-qrd: add QRD8550 
Add a minimal DTS for the new QRD8550 board - a mobile-like development
board with SM8550.  Serial, UFS and USB should be working.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230210163844.765074-2-krzysztof.kozlowski@linaro.org
 2023-03-14 19:30:46 -07:00
Abel Vesa
749078e38e arm64: dts: qcom: sm8550-mtp: Add eUSB2 repeater node 
Add the PMIC eUSB2 repeater node and add the usb-repeater
property to the eUSB2 PHY to allow it to be controlled by the
PHY driver.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208190200.2966723-8-abel.vesa@linaro.org
 2023-03-14 19:30:46 -07:00
Neil Armstrong
fdaa922585 arm64: dts: qcom: pm8550b: Add eUSB2 repeater node 
Add nodes for the eUSB2 repeater found on the pm8550b SPMI PMIC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208190200.2966723-7-abel.vesa@linaro.org
 2023-03-14 19:30:46 -07:00
Abel Vesa
32734bbd18 arm64: dts: qcom: sm8550: Fix PCIe PHYs and controllers nodes 
First, move the pinctrl related propeties out from SoC dtsi and into the
board dts and add blank lines before status properties in the PHY nodes
to be consistent with the rest of the nodes. Then drop the pipe clock
from the controller nodes. Rename the aggre0 and aggre1 clocks to more
generic noc_aggr, and then the cnoc_pcie_sf_axi to cnoc_sf_axi. Add the
cpu-pcie interconnects to both controller nodes. Rename the pcie1 second
reset to link_down and drop the unnecessary enable-gpios. Switch the aux
clock to GCC_PCIE_1_PHY_AUX_CLK for the pcie1 PHY and drop the aux_phy
from clock-names. Also rename the nocsr reset to phy_nocsr. With this
changes we are now in line with the SC8280XP bindings.

Fixes: 7d1158c984 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-12-abel.vesa@linaro.org
 2023-03-14 19:30:22 -07:00
Johan Hovold
5fef1b434a arm64: dts: qcom: sc8280xp-x13s: enable rtc 
The Lenovo X13s firmware does not implement the UEFI time runtime
services so the RTC in the PM8280K PMIC needs to be accessed directly.

To complicate things further, the RTC control and time registers are
read-only on this platform so an offset must be stored in some other
machine-specific non-volatile memory which an RTC driver can take into
account when reading or updating the time.

The UEFI firmware (and Windows) use a UEFI variable for this:

	882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo

but the offset can only be accessed via the Qualcomm UEFI Secure
Application residing in the TEE as the firmware does not implement the
variable runtime services either.

While it is possible to access this UEFI variable from Linux on the
X13s, this requires using a fairly complex and reverse-engineered
firmware interface. As the only benefit of doing so is to make sure that
the UEFI (Windows) and Linux time never gets out of sync, it seems
preferable to use the PMIC scratch registers for storing an offset
instead. This also avoids flash wear in case of RTC drift, etc.

So instead of using the UEFI RTC offset, reserve four bytes in one of
the PMIC SDAM scratch-register blocks to hold the RTC offset.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230202155448.6715-23-johan+linaro@kernel.org
 2023-03-13 12:38:09 -07:00
Johan Hovold
e67b45582c arm64: dts: qcom: sc8280xp-crd: enable rtc 
The SC8280XP CRD firmware does not implement the UEFI time runtime
services so the RTC in the PM8280K PMIC needs to be accessed directly.

To complicate things further, the RTC control and time registers are
read-only on this platform so an offset must be stored in some other
machine-specific non-volatile memory which an RTC driver can take into
account when reading or updating the time.

The UEFI firmware (and Windows) use a UEFI variable for this:

	882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo

but the offset can only be accessed via the Qualcomm UEFI Secure
Application residing in the TEE as the firmware does not implement the
variable runtime services either.

While it is possible to access this UEFI variable from Linux on the CRD,
this requires using a fairly complex and reverse-engineered firmware
interface. As the only benefit of doing so is to make sure that the UEFI
(Windows) and Linux time never gets out of sync, it seems preferable to
use the PMIC scratch registers for storing an offset instead. This also
avoids flash wear in case of RTC drift, etc.

Also note that setting variables using this interface does not work on
at least one CRD for reasons not yet known.

So instead of using the UEFI RTC offset, reserve four bytes in one of
the PMIC SDAM scratch-register blocks to hold the RTC offset.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230202155448.6715-22-johan+linaro@kernel.org
 2023-03-13 12:38:09 -07:00
Johan Hovold
d6dbbda37a arm64: dts: qcom: sc8280xp-pmics: add pmk8280 sdam nvram 
Add one of the PMK8280 SDAM blocks which can be used to store an RTC
offset.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230202155448.6715-21-johan+linaro@kernel.org
 2023-03-13 12:38:09 -07:00
Johan Hovold
009d936f15 arm64: dts: qcom: sc8280xp-pmics: add pmk8280 rtc 
The PMK8280 has an RTC which can also be used as a wakeup source.

Note that the RTC can not be disabled and updating the time is not
permitted either. Instead an offset can be stored in some other machine-
specific non-volatile memory which a driver can take into account.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230202155448.6715-20-johan+linaro@kernel.org
 2023-03-13 12:38:09 -07:00
Richard Acayan
17289c0165 arm64: dts: qcom: sdm670: add opps for peripherals 
The interconnects are now in place. Add Operating Performance Points for
them to allow the kernel to properly manage them.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230201010020.84586-3-mailingradian@gmail.com
 2023-03-13 12:36:36 -07:00
Bhupesh Sharma
96ce9227fd arm64: dts: qcom: sm6115: Add remoteproc nodes 
Add the adsp, cdsp and modem remoteproc nodes to sm6115.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[bjorn: Extended regs to match #address/size-cells to 2]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230128054256.2100501-1-bhupesh.sharma@linaro.org
 2023-03-13 12:34:25 -07:00
Bartosz Golaszewski
d97ba0b040 arm64: dts: qcom: sa8155p-adp: enable the GNSS high-speed UART 
Enable the high-speed UART port that's connected to the GNSS controller
on the board.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309143551.200694-3-brgl@bgdev.pl
 2023-03-13 12:11:27 -07:00
Bartosz Golaszewski
10d900a834 arm64: dts: sm8150: add the QUPv3 high-speed UART node 
Add the high-speed UART node to the dtsi for sm8150.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309143551.200694-2-brgl@bgdev.pl
 2023-03-13 12:11:27 -07:00
Linus Torvalds
fe15c26ee2 Linux 6.3-rc1 2023-03-05 14:52:03 -08:00