The OTG driver disables the gadget device when the cable is
removed, so there is no need to check if the cable is plugged
before touching registers.
Change-Id: I0b1a3a8b07560d3eca2e2e25574b5219e3373808
Signed-off-by: Benoit Goby <benoit@android.com>
On suspend, dr_controller_stop disable interrupts and on resume, interrupts
are disabled until dr_controller_run is called, so it is safe to call
fsl_udc_clk_suspend/resume with interrupts and the spinlock unlocked.
Change-Id: I33618295ea096a4bfd796d1a07dfc9722e7786b0
Signed-off-by: Benoit Goby <benoit@android.com>
The upstream DC needs to be clocked for accesses to HDMI to not hard lock the
system. Because we don't know if HDMI is conencted to disp1 or disp2 we need
to enable both until we set the DC mux.
Change-Id: Iab7df9911aa9034ea559896850787e4eff3237d7
Signed-off-by: Erik Gilling <konkers@android.com>
Save/restore SLINK_COMMAND_0 register.
Wait for in-progress transactions to complete before suspend.
Reject and WARN_ON transactions when suspended.
Change-Id: I0527781f0bf95781afa3a35a68282cde2f0189ae
Signed-off-by: Todd Poynor <toddpoynor@google.com>
If the device connected to a port has out-of-band wakeup
signaling, the phy and controller may be powered off on bus suspend.
Change-Id: Ia206f05d01160411b97aefa83045cd759d35b66d
Signed-off-by: Benoit Goby <benoit@android.com>
the panjit touchscreen needs to be reset when returning from
deep sleep mode; add a platform data structure to specify
the reset GPIO.
perform the reset during _probe, since the code already needs
to exist for _resume
delete a bunch of unused preprocessor defines
Change-Id: I71ae65dec45710b0eab4625036edf75064d4cc2b
Signed-off-by: Gary King <gking@nvidia.com>
If we use an OTG driver, the driver will detect VBUS changes and notify
the gadget driver through vbus_session. Enable/disable the gadget driver
in vbus session so that there is no need to check the OTG state on every
interrupt.
Change-Id: I617ad5742be2632b2257b71314db8f330be463d5
Signed-off-by: Benoit Goby <benoit@android.com>
There is no need anymore to check the OTG state on every interrupts and
use a work thread.
Moved the suspend code from usb_phy.c as this is ehci specific.
Change-Id: I523baab1476323a35360b1d802088370e42d0fd7
Signed-off-by: Benoit Goby <benoit@android.com>
Tegra quirk: The PORT_RESET bit in PORTSC1 does not need to be cleared
and there is no need to wait for it to clear. The bit will automatically
change to 0 when the bus-reset sequence is done and an interrupt will be
generated.
Change-Id: I645417013af46785a249096ebc06a1f688228d94
Signed-off-by: Benoit Goby <benoit@android.com>
The SDHCI controller specifies a maximum SDCLK speed of 48MHz, which is
now in agreement with the platform clock, and so the SDHCI host max_clk
no longer needs to be overriden.
Change-Id: Ie8c7f643d956cfd1bb83675708336278482c40d8
Signed-off-by: Todd Poynor <toddpoynor@google.com>
add a driver for the hardware watchdog timer embedded in NVIDIA
Tegra SoCs
Change-Id: I45bc829f26f350143d5a07e1f4ddc46d24f3a54c
Signed-off-by: Gary King <gking@nvidia.com>
only reset the controller when doing so won't also reset the phy (Tegra quirk)
Change-Id: I549a18977d0d5ebfa12c32016aa9e6bffaa8643c
Signed-off-by: Gary King <gking@nvidia.com>
driver supports the MGG1010AI06 and EGG1010AI06 capacitive touch panels
Change-Id: I038030bf4c9acbd0d3d504427a32f4e46632c115
Signed-off-by: Gary King <gking@nvidia.com>
drivers/mmc/core/mmc.c:228: error: ‘SZ_256K’ undeclared (first use in this function)
Introduced by:
mmc: subtract boot sectors from disk size for eMMC 4.3+ devices
(SZ_* doesn't exist on anything but arm)
Change-Id: I981217adea4ef56bf870562b6711488f3f4bf830
Signed-off-by: Olof Johansson <olof@lixom.net>
initialize baud rate and configuration settings to safe default values
when receive DMA is in use, so that the DMA request may be enqueued at
initialization time
re-enqueue the receive DMA buffer immediately it is dequeued by the
DMA threshold callback and the receive ISR, rather than waiting for the
DMA complete callback
originally fixed by Gary King <gking@nvidia.com>
Fixing tx trigger level setting:
On tegra uart, the FCR setting for different tx trigger level
is not same as the 16550 tx trigger level setting. The tegra
uart have the setting in reverse direction on tx fifo attention
level:
b00 for 16 bytes attention level.
b01 for 8 byte attention level.
b10 for 4 byte attention level
b11 for 1 byte attention level.
The rx trigger attention level match with the standard uart
FCR register setttings.
Also fixing the typo in code when setting DTR.
originally fixed by Laxman Dewangan (ldewangan@nvidia.com)
Change-Id: Iea00478f143e61c604828035c6c92d614fa7cccb
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
tegra_start_tx was called directly by the serial core, as
well as from dma and serial interrupts to queue the next
block of data. Separate out the "queue next data"
functionality into tegra_start_next_tx.
Also fixes TX PIO by adjusting FIFO sizes and prevents
last characters from getting lost by spinning on TEMT
before disabling clocks.
Change-Id: If8ce15490f77dcbde48f1e64959d5c3f0ec35120
Signed-off-by: Colin Cross <ccross@android.com>
the csd sector count reported by eMMC 4.3+ cards includes the boot
partition size; subtract this from the size reported to the disk
since the boot partition is inaccessible
Change-Id: I601b83aa0159b7aa446409ea8c945b256dd0b5b1
Signed-off-by: Gary King <gking@nvidia.com>
