stress test:
1. Antutu, use governor simpleondemand
2. Need for Speed, use governor simpleondemand
3. Glmark2, use userspace, scanning frequency
Change-Id: Ibe27380e582b193d900b0d55da3567ce553c32df
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
To support ddr frequency scaling function, we need
enable dmc and dfi node.
Change-Id: I84ea6bff679365d86937ff10bcdf466ea31901fb
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add support to check initial rate and voltage according to opp table,
limit rate and update voltage according to temperature.
Change-Id: I146787e07be63f9f7eeaf93e8a1594809dcc23e8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
DRM_FORMAT_NV20 and DRM_FORMAT_NV30 is a 2 plane format suitable for
linear layouts, this two format is similar to NV15 has no padding
between component, but NV15 is 4:2:0 sub-sampling, NV20 is 4:2:2
sub-sampling and NV30 is no-sampling.
The '20' and '30' suffix refers to the optimum effective bits per
pixel which is achieved.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I84da7e03125e675f274c6307128b4b7b307767cc
for example:
Use CLuster0 as cursor win for vp0.
&vp0 {
cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>;
};
Change-Id: I10f7921928fbf7ff803c55a95cbce62df658fbed
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
We have some plane not registered to drm core(Such as cluster
plane on some linux system), so they don't have pstate.
And also we don't need to check plane state for oetf for
a inactived plane(has no fb).
Change-Id: I909b665397c3df530ff0f466e0d654dcbb3f1a40
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
keep sdr2hdr result consistent between VOP and GPU
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3ef6b289978d4b0c083d99e93d97a95b2e7f0b25
Add a BACKGROUND property for each crtc.
8 bit for every color channel(r/g/b/y/u/v).
Change-Id: I9439bf16a8142e936508e843cc25b6263e2f661d
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Fixes: 8c59d20b75 ("drm/rockchip: vop2: Add color key support")
Change-Id: I449f32eb9e69297b2c37feb85611a550310f2304
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
the fs raw bit will be cleared by vop2_isr() fs irq and lead to
vop2_wait_for_fs_by_raw_status() time out, so we use
vop2_wait_for_fs_by_done_bit_status() to wait done bit from 1 to 0 is
more reliable.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ice35fb9bfe6c2ef7a49496b15b9f58bf93e95d4e
We thought when userspace switch hdmi to hdr mode, it must
give vop a hdr plane, but We meet a case: composer give
vop only one sdr plane, but switch hdmi to hdr mode.
so we don't check the plane number for sdr2hdr_en;
Change-Id: I4804a88321af84328735d6499ac9df610bf2cb85
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
win_mask is more safe than plane_mask on crtc_state,
because crtc_state may changed by many interface.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I886c8e1e1c0505e46292721de05d9be7c167d956
we must make sure the port_mux configuration is take effet
before configure a window that is moved from another VP.
Change-Id: I4ca581292e08ef30cc4b6eb47aef02e678f38a66
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
port_mux register is shared by all the three(four on rk3588)
video ports, and the config done vsync is controlled by
layer_sel_regdone_sel bits.
We must make sure the previous configuration is take
effect, when change port_mux for another vp.
Change-Id: Ic4bd58f52760080f2f264f37cc6f01a9cd58939f
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
There maybe a case a new wb commit is commit when
the last wb has not completed, this may override
the fs_vsync_cnt.
So counter vsync for every wb job independently.
Change-Id: I8e8c527a49252dcc4b0b1ff591523de5a33ae5ba
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
If the layer pass through layer mix is unused, we need to disable alpha,
at this time, the layer mix only used to transfer alpha to next mix.
Change-Id: Ibd469b4fb61b41480297bc20c346e9ceefa61fc7
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This is for mipi dsi on rk356x: there
is a hold signal from mipi dsi to
vop.
Mipi dsi may trigger the hold signal
when send dsi command or switch between
video mode and command mode.
vop may run into an unexpected situation if this hold
signal is rise when vop is running.
So when mipi dsi switch between video mode
or command mode, or send a dsi command, it
should set vop in stanby state.
Change-Id: I80e456d3416518436045ae8e0eec215c22b111a3
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
