If flow control is configured in DTB, the priority is the highest,
otherwise the default value in the code is used.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I21afeb537426473d6edf7ce40317cdaf99d64a93
Fixes: 1df11488e9 ("mfd: rk808: support power off system in syscore shutdown")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I0167cdda639ed9b44ad09c25937e652e92a3a267
1. update init registers setting
2. nvp6188 do not stream after writing registers setting
3. support detect fmt change when hotplug ahd camera
4. support 1600x1300 ahd camera input
Change-Id: I26d51e5eede8d956065bcb9d94359c7d815c9f44
Signed-off-by: Jason Song <sxj@rock-chips.com>
Fix no signal when hdmi switch from hdmi2.0 tv to
hdmi1.4 tv.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ie90edcf737f204568bcac233acab9aa6046c20e3
1. Simplify some code.
2. Use mpp_time_diff_with_hw_time to get hw time.
3. Loop to get task from pending list after task enqueue hw
successfully.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Icfecbc6b620efbf410076ca3765fb921d1665260
For RK3588 and RK3568, the hactive of video timing must
be 4-pixel aligned.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I2485e27420b365104c5c876708600fb59189e1af
If other display port such as edp bind failed, hdmi
will re-bind. The conditions for determining whether
uboot logo is enabled are unreliable. Changing judgment
flag to an unused reg.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I2b634ae159934bb62ea1a08864bf8b1b9cbb479d
Since there is no txdone irq in the Rockchip mailbox IP, invoking
mbox_chan_txdone()/mbox_client_txdone() after mbox_send_message()
to tick the TX would be free the active request which have not been
sent out if the controller returned the EBUSY state before. So amend
the txdone method to polling to fix it.
The TX polling interval can specify in DT with
"rockchip,txpoll-period-ms" property, if it is not set, the driver
would hardcode to 5 milliseconds.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ic26d3245dd8bd90ebad30fce9ece2f4452814f7f
Specify TX Done polling interval in milliseconds with the
"rockchip,txpoll-period-ms" property.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I91f25e6b5e6ef05cf90147b2e609c71c6ed61df7
* Add nbuf memory support
* Add rknpu session for each instance
* Add multi core irq status timeout log
* Fix job run count error
Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Change-Id: I408e535fa1b3f8c853682a8ebaa245e3d7c188fb
on vehicle evb, sdio wifi power on delay recommend 10ms at least.
Signed-off-by: Jason Song <sxj@rock-chips.com>
Change-Id: I0d489b080f0a6323eb14261eaf557e3e3f0e13ee
In some case, the hpd is detected but the aux is not ready. It's
better to detect aux status before get link info from dpcd.
When the dptx send a aux request transaction, the dptx's max
aux timeout value is 3.2 ms, set the timeout value as 10ms
is enough.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Id878c0c2c1c5690ac08bad477ea96ac12b674edb
ALSA core blocks userspace for 10 seconds for PCM R/W default.
Consider the situation BT-slave which acts as SLAVE mode, when
BT-master offline sometime, the CLK lost, user have to wait the
core timeout(10s), it's quite bad experience.
This patch allows userspace to override the WAIT_TIME to recover
more quickly from terminal audio stream. especially for stream
which have no mechanism to detect the LINK offline.
Usage:
/# amixer -c 0 contents | grep Wait
numid=43,iface=PCM,name='PCM Read Wait Time MS'
numid=44,iface=PCM,name='PCM Write Wait Time MS'
/# amixer -c 0 cset numid=43 500
numid=43,iface=PCM,name='PCM Read Wait Time MS'
; type=INTEGER,access=rw------,values=1,min=0,max=10000,step=1
: values=500
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I73e98d54388a50672c5ed710db448cd13c0e1098
After FS idle, should wait at least 2 BCLK cycle to make sure
the CLK gate operation done, and then disable mclk.
Otherwise, the BCLK is still ungated. once the mclk is enabled,
there maybe a risk that a few BCLK cycle leak. especially for
low speed situation, such as 8k samplerate.
The best way is to use delay per samplerate, but, the max time
is quite a tiny value, so, let's make it simple to use the max
time. the max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK)
udelay(40);
Should wait for one BCLK ready after DIV and then ungate clk to
achieve the clean clk. the max BCLK cycle time is:
15.6us @ 8K-8Bit (64K BCLK)
udelay(20);
Increase the max timeout to 1ms to fix FS idle failed. because
it's not enough for 8k samplerate.
rockchip-sai ff810000.sai: Failed to idle FS
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ia9da291dd8586236bb32cc0376a6de389f2f0a40
This patch add property 'rockchip,no-dmaengine' to
support register DAI without PCM, and it's usually
used for Multi-DAIs which combine DAIs into a union one.
Change-Id: I4e0da8fae2c692601e05118442218de0f7b4efee
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch add support for keeping BCLK / FSYNC always on.
it's required by some devices, such as HDMI, PA, etc.
For example: on HDMI situation
There are some TVs require maintaining N/CTS packets or AUDS
packets to keep audio logic active, otherwise, the first tone
may be lost.
In order to optimize the user experience, we need to ensure
continuous transmission of N/CTS and AUDS packets from the
HDMI-TX, so that the SINK TV devices can maintain audio logic
activation, promptly process audio data, and achieve the
completeness of the first tone.
We init a 48k I2S-STANDARD clock timing as default.
Change-Id: I298b0ad2d53bdc41927f567c2af481f2a0bd5422
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
There is a issue of stuck during dual-core collabration,
and the hw timeout count will be blocked by default,
and only soft timeout can be triggered to exit.
However, the soft timeout is too loog, so config reg to not mask the hw
timeout.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: If801b8ba3b463094ea497fae829f772de7ade382
In some platform, can not do pmu_idle_request before cru reset.
Resetting without pmu_idle_request while the hw is running
will result in a bus err.
So stop hw first before cru reset to prevent the issue.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I62ace147a0d72adb774fed989b34c7bf22af48ac
