Some platform like rk3288,rk3368,px30, we need to config grf
register to invert dclk polarity when connector is rgb or lvds.
Change-Id: I9ef9ce09f050ee42c0543d415a9baac1f50a0848
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Since some special hardware or panel need to invert dclk,
so we add dclk invert config at dts display timing node:
dts sample:
display-timings {
timing0: timing0 {
...
pixelclk-active = <1>;
...
}
}
Change-Id: I64f053ecda0f607bdd6fd392a0922489502ac274
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
1 move pinctrl into board level dts file.
2 remove pinctrl for sleep state.
in sleep state we do not change pin control and keep the pin control
in otp state, which is used by atf as a flag to control pmic's state.
Change-Id: Ib68b20d4f4ba79d99255f1deb509ff8a741deef2
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Fixes: 6882654464 ("regulator: core: Add support to limit min_uV during system startup")
Change-Id: Ie281f77d9e36cd8bc72b075bb7b18b9cb0eb7ec5
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reduce about 8ms for led driver initialization time
before:
initcall is31fl32xx_driver_init+0x0/0x20 returned 0 after 14832 usecs
after:
initcall is31fl32xx_driver_init+0x0/0x20 returned 0 after 6270 usecs
Change-Id: I3154efa154a484ccf8f9974c8148ff9895b1f68a
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Force bootargs for bring up rk3288-linux with RKIMG_BOOT.
Change-Id: I43d03e51abddeb4c29fb4c94bbd2dba774b4abe5
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Single entry is for target voltage and three entries are for
<target min max> voltages. Change cpu opp-microvolt form one entry to
three entries and set maximum acceptable voltage to a high value so that
regulator device can supply multiple consumers at the same time.
Change-Id: I72e2efb9828432ee29773c8e1939a59062127ff7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
If dmc node doesn't contain 'system-status-freq' and auto-freq is disabled,
devfreq feature won't be added and only to adjust voltage according to opp
table.
Change-Id: Iaf9d9f61938babff2e08719e2285a8554cfa9389
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Now a regulator device can supply multiple consumers at the same time,
if a consumer starts and set a low voltage, another consumer doesn't
start in kernel but has been set a high frequency in bootloader will
abort.
This patch Adds support to limit min_uV during kernel startup to make
sure the voltage can suit the needs of all consumers.
Change-Id: Ibd16a8e44916798021e2470c90a8e3488df206f4
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add support hp-ctl gpio for amic board, and rename
to spk-ctl from dtsi file. Usually, we should assign
these output ctl gpios according to the specific
product type.
Change-Id: Icf0c29f61bed3c0f48069b9e38ddf47d921fed26
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We need to configure each ADC in parallel as much as
possible. The infos from vendor, we add some new
registers to make effect better:
1/ optimize the flows for enable/disable ADC/DAC flows
2/ add support fade-out digital gains for de-pop
3/ many updates
Change-Id: I2e72451201010de96e7dc5c22ff3384ce71767ea
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
When PMIC irq occurs, regmap-irq.c will traverse all PMIC child
interrupts from low index 0 to high index, we give fall interrupt
high priority to be called earlier than rise, so that it can be
override by late rise event. This can helps to solve key release
glitch which make a wrongly fall event immediately after rise.
Change-Id: Ieda1d6fd3c50cc36742a4740504ec7ce12ea509b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Setting inno phy config table in dts. According to tmds clock range, phy
config data can be chosen. We can also filter some video modes which
tmds clock out of range we set.
Change-Id: I666c825921877fe2cdf45c2ccd1415815a4b7715
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
For hotplug device the crtc->primary->fb should be equal to
fb_helper->fb, otherwise the following path will return false
and lead to connect state error:
->hotplug
->output_poll_changed()
->drm_fb_helper_hotplug_event()
->drm_fb_helper_is_bound()
after user space beging, the above path can return false, because
sometimes user space wants everything disabled, don't steal the display
if there's a master, so we set crtc->primary->fb point to the original
fb when drm_open.
Change-Id: I5343978ce602324dbdc3125b6b98a7b4233149ab
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The reason to implement shutdown is for the fake shutdown on the box
product. but after implement this function, panel will still display
overlay plane for about two second when power off. so we directly
close crtc instead of rockchip_drm_sys_suspend() when shutdown.
Change-Id: I60ed3e541e022ad828fd535828fe264aabd40ecb
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
When a usb device disconnects in a certain way, dwc2_queue_transaction
still gets called after dwc2_hcd_cleanup_channels.
dwc2_hcd_cleanup_channels does "channel->qh = NULL;" but
dwc2_queue_transaction still wants to dereference qh.
This adds a check for a null qh.
(am from https://patchwork.kernel.org/patch/7245251/)
Change-Id: Ia9c7f5febe0bb6f0123cfc85c90beb9fc1d80bdd
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
some low solutation SPI panel, the display content should be
send through the SPI interface, so add to get the kernel virtual
address, which can be accessed by cpu and SPI interface.
Change-Id: I9823162e682819309bf61d3b132eb452b73fdd3a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Pre PLL pclk_dividera value range is from 1 to 31, but the default
value of register 0xe0 on 3229 is zero. To avoid div zero error,
we take the divider value as one.
[<c0110070>] (unwind_backtrace) from [<c010bcbc>] (show_stack+0x20/0x24)
[<c010bcbc>] (show_stack) from [<c040f56c>] (dump_stack+0x80/0xa0)
[<c040f56c>] (dump_stack) from [<c010bbf4>] (__div0+0x20/0x28)
[<c010bbf4>] (__div0) from [<c040d62c>] (Ldiv0_64+0x8/0x18)
[<c040d62c>] (Ldiv0_64) from [<c043f310>] (inno_hdmi_rk3228_phy_pll_recalc_rate+0x104/0x114)
[<c043f310>] (inno_hdmi_rk3228_phy_pll_recalc_rate) from [<c043efac>] (inno_hdmi_phy_clk_recalc_rate+0x30/0x3c)
[<c043efac>] (inno_hdmi_phy_clk_recalc_rate) from [<c0980c00>] (clk_register+0x438/0x64c)
[<c0980c00>] (clk_register) from [<c0980e68>] (devm_clk_register+0x54/0x94)
[<c0980e68>] (devm_clk_register) from [<c0440028>] (inno_hdmi_phy_probe+0x24c/0x378)
[<c0440028>] (inno_hdmi_phy_probe) from [<c0566424>] (platform_drv_probe+0x60/0xac)
[<c0566424>] (platform_drv_probe) from [<c05645bc>] (driver_probe_device+0x120/0x2a8)
[<c05645bc>] (driver_probe_device) from [<c05647bc>] (__driver_attach+0x78/0x9c)
[<c05647bc>] (__driver_attach) from [<c0562a28>] (bus_for_each_dev+0x84/0x98)
[<c0562a28>] (bus_for_each_dev) from [<c05640d0>] (driver_attach+0x28/0x30)
[<c05640d0>] (driver_attach) from [<c0563c5c>] (bus_add_driver+0xdc/0x1f8)
[<c0563c5c>] (bus_add_driver) from [<c056533c>] (driver_register+0xac/0xf0)
[<c056533c>] (driver_register) from [<c0566364>] (__platform_driver_register+0x40/0x54)
[<c0566364>] (__platform_driver_register) from [<c122af4c>] (inno_hdmi_phy_driver_init+0x18/0x20)
[<c122af4c>] (inno_hdmi_phy_driver_init) from [<c0101ad4>] (do_one_initcall+0x114/0x1c8)
[<c0101ad4>] (do_one_initcall) from [<c1200ef0>] (kernel_init_freeable+0x1ac/0x280)
[<c1200ef0>] (kernel_init_freeable) from [<c0c5e4c8>] (kernel_init+0x18/0x11c)
[<c0c5e4c8>] (kernel_init) from [<c0107550>] (ret_from_fork+0x14/0x24)
Change-Id: Ib61fbd87547d3316e9ed5b564e291b6c15d93cdd
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch fix the following clang warning:
[clang]drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1255:3:
warning: Value stored to 'delay' is never read
Change-Id: I8c70975e1bc2b24a78d0934ccefc9d67fe3a5da9
Signed-off-by: William Wu <william.wu@rock-chips.com>
In dwc_otg_hcd_endpoint_disable(), the hc_regs is initialized
to NULL, but never assign a host channel reg address to it,
so the chdis operation can't be handled for ever.
This patch gets a host channenl reg address for hc_regs via
qh->channel->hc_num.
Change-Id: I5917df1975000876d28868ed51e218489ed3d209
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reduce the otg schedule delay time from 6s to 1s to do
the first time usb charger detection earlier when power
on system with usb cable connect to PC USB. Because the
usb connection willed be disconnectted during usb charger
detection.
And the patch also makes the phy detect the usb disconnetion
more quickly after usb cable plug out.
Change-Id: I9b55317ab3592f517fdf590fea85c4ed403bbd8d
Signed-off-by: William Wu <william.wu@rock-chips.com>
