f3d9c312b8 ("Implement memory_state_time, used by qcom,cpubw")
New driver memory_state_time tracks time spent in different DDR
frequency and bandwidth states.
Memory drivers such as qcom,cpubw can post updated state to the driver
after registering a callback. Processed by a workqueue
Bandwidth buckets are read in from device tree in the relevant qualcomm
section, can be defined in any quantity and spacing.
The data is exposed at /sys/kernel/memory_state_time, able to be read by
the Android framework.
Functionality is behind a config option CONFIG_MEMORY_STATE_TIME
Change-Id: Ic3b0b631efd697713360f193ede440cd9ad3bc29
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
f3d9c312b8 ("Implement memory_state_time, used by qcom,cpubw")
New driver memory_state_time tracks time spent in different DDR
frequency and bandwidth states.
Memory drivers such as qcom,cpubw can post updated state to the driver
after registering a callback. Processed by a workqueue
Bandwidth buckets are read in from device tree in the relevant qualcomm
section, can be defined in any quantity and spacing.
The data is exposed at /sys/kernel/memory_state_time, able to be read by
the Android framework.
Functionality is behind a config option CONFIG_MEMORY_STATE_TIME
Change-Id: I4391cc3ed42c9f332bce4a7809c6f120e2798dae
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
If we power off the SoC LOGIC rail in S3, we can find that the
Type-C PHY can't initialize correctly after system resume with
error log looked like this:
phy phy-ff800000.phy.9: phy poweron failed --> -110
dwc3 fe900000.dwc3: failed to initialize core
dwc3: probe of fe900000.dwc3 failed with error -110
It's because that the field of usb3tousb2 in GRF_USB3PHY0/1_CON0
is reset to 1 after power off the SoC LOGIC, which means that the
pipe interface is blocked between Tpye-C PHY and usb3 controller.
And after system resume, the rockchip_usb3_phy_power_on() will call
the tcphy_cfg_usb3_to_usb2_only() to clear the usb3tousb2 bit and
enable the usb3 host again. If we clear the usb3tousb2 bit before
pipe ready, it may cause waiting for pipe ready timeout.
Note that the RK3399 TRM suggests that we should keep the whole usb3
controller in reset for the duration of the Type-C PHY initialization.
However, it's hard to assert the reset in the current framework of
reset. And according to the TRM, it doesn't require that we should
clear the usb3tousb2 bit before pipe ready. So let's enable the usb3
host after pipe ready to avoid the Type-C PHY initialization failure.
BUG=b:62644399, chromium:783464
TEST=run suspend_stess_test on Scarlet, usb device can work after resume
Change-Id: Ie597cbe35568c390460aa2fdbad0e66c6104c8d2
Reviewed-on: https://chromium-review.googlesource.com/896908
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
If we power off the SoC LOGIC rail in S3, it seems that the host
controller comes back in an undefined state, such that the Type C PHY
can't initialize correctly. We need to toggle the USB3-OTG reset before
trying to initialize the PHY, or else it often times out.
Note that the TRM suggests we should be asserting this reset for the
duration of the PHY initialization, but we're still skeptical about
that, and we haven't yet found a case where this seems to have mattered.
Besides, this approach is much easier.
The dwc3 core is going to reinitialize the controller at suspend/resume
anyway (including a "soft reset"), so it should be safe to do this,
regardless of whether the system actually powered off the USB logic.
For hygiene's sake, it's good to wait some small bit of time in between
asserting/de-asserting this reset. Might as well apply this to both
instances of this reset.
BUG=b:62644399
TEST=suspend/resume scarlet with LOGIC disabled in S3; USB comes back OK
also test suspend/resume on kevin for USB regressions
Change-Id: I5b5354d0fb9c7ed9d2c9044ddfbb5f7709884fb7
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/877404
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Base on the rise time of scl test, the scl frequecny could be
increased to 400k.
Change-Id: I17f858b28ed11992411c52e5f83424b0187d097c
Signed-off-by: David Wu <david.wu@rock-chips.com>
Base on the rise time of scl test, the scl frequecny could be
increased to 400k.
Change-Id: I9af57e13a97f0866ec4f0dd295f9bcf4cbeee304
Signed-off-by: David Wu <david.wu@rock-chips.com>
4ed084e489fd ("Move CONFIG_AIO to android-base.")
CONFIG_AIO has legitimate use for the functionfs
driver, which is used with adb and mtp. It is now
required to be enabled for better performance
with those services.
Change-Id: I52d05c734a25b35e012666b010b2ee5426915094
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
4ed084e489fd ("Move CONFIG_AIO to android-base.")
CONFIG_AIO has legitimate use for the functionfs
driver, which is used with adb and mtp. It is now
required to be enabled for better performance
with those services.
Change-Id: I631fac8e56ea16711f0cc05297140dc59c9fb581
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
6e30a9a158bd ("remove CONFIG_PM_AUTOSLEEP from android-base.cfg")
Autosleep is no longer used by Android.
Change-Id: Ia024dbb6343abd8e1016febc08251dc5dc7badc1
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
6e30a9a158bd ("remove CONFIG_PM_AUTOSLEEP from android-base.cfg")
Autosleep is no longer used by Android.
Change-Id: I7ff5c40a8cdfbe9e67019bc859eb940fae2b6c4f
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Reading rk1000's register to see whether uboot logo was on.
Change-Id: Iee6d15213f16ccd59136a5cf4f4017f5cd40ab62
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Removing ports so that uboot display subsystem can get
rk1000 as panel.
Change-Id: If12c30bb7d1bd382ed969534687234aa79b8dd04
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
cc756e682c ("ANDROID: android-base.cfg: remove USB_OTG_WAKELOCK")
CONFIG_USB_OTG_WAKELOCK is currently somewhat outdated
and as such is not applicable to all Android devices. Until
it is brought up to date, remove it from the base Android
kernel configuration.
Change-Id: I4d6a2ba78ddc9210bc949ee2ecc5182a4814715d
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
cc756e682c ("ANDROID: android-base.cfg: remove USB_OTG_WAKELOCK")
CONFIG_USB_OTG_WAKELOCK is currently somewhat outdated
and as such is not applicable to all Android devices. Until
it is brought up to date, remove it from the base Android
kernel configuration.
Change-Id: Id112f1e692fce021b8ab5437ae7811c216c8d272
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
bc86c1de1d ("ANDROID: android-base.cfg: remove NETFILTER_XT_MATCH_QUOTA2_LOG")
There are currently a couple different implementations for this
functionality. Until things are unified, remove the requirement
for this kernel config.
Change-Id: Ia3f515452871118dab4b8688ff9fd16e87beb9b6
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
bc86c1de1d ("ANDROID: android-base.cfg: remove NETFILTER_XT_MATCH_QUOTA2_LOG")
There are currently a couple different implementations for this
functionality. Until things are unified, remove the requirement
for this kernel config.
Change-Id: Ibbe93ae71d4b7512be397e689abc36ba51011b30
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
97841e574a ("ANDROID: android-base.cfg: remove CONFIG_CGROUP_DEBUG")
This config option is not required by Android.
Change-Id: I2c57f98f94465d56aac60fe12b9b4d0a42d42242
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
97841e574a ("ANDROID: android-base.cfg: remove CONFIG_CGROUP_DEBUG")
This config option is not required by Android.
Change-Id: Ica7ed956e2340d5fd8756a400d13725799857423
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
When a disabled iommu node is referenced by a master which cause the previous iommu nodes
removed from the iommu group, finally cause kernel crash, return -ENODEV instead -EPROBE_DEFER
if iommu node disabled can fix this issue
Change-Id: I3adf3f4119ff6fff0a2068301338813f5aca8969
Signed-off-by: Simon Xue <xxm@rock-chips.com>
RK322x is a 32-bit SoC, the length of register is 32-bit.
Change-Id: I3fe506b0f9c7f8ec70a56863f95decdc12e61e85
Signed-off-by: Liang Chen <cl@rock-chips.com>
