Support rockchip,rk1808-usb2phy-grf for rk1808 board.
Change-Id: I9f3cc8300bf2653689c07734b81bcf7ff9aac4eb
Signed-off-by: William Wu <william.wu@rock-chips.com>
Support rockchip,rk1808-dwc3 for rk1808 board.
Change-Id: I68d9233e8cdf4704b54eb1fe2f17baf43ab6caf5
Signed-off-by: William Wu <william.wu@rock-chips.com>
When the pin is set as an iomux value that is outside its range,
it should return a failure, otherwise it may be overwritten with
incorrect value.
Change-Id: I381d9f5bf6f4bfa7d0512350e6b051bebf513d3e
Signed-off-by: David Wu <david.wu@rock-chips.com>
It looks better that handle the hight pass filter (HPF)
on the user space, therefore, disable it by codec.
By the way, add HPF dapm controls if someone need to
enable HPF cut-off.
Change-Id: Id8d5f4f84a8ad9909d6aa35c484e955ab92bffed
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We find an usb phy 480MHz clk prepare fail issue on PX30/RK3326
platforms with RK819 PMIC. On PX30/RK3326 platforms, we set the
usb480m clk to critical because GPU 480M is from usb480m and the
source clocks should be always on. And the usb phy 480MHz clk is
parent of usb480m clk, so the clk framework will prepare the usb
phy 480MHz clk when register it.
This logic works well if the usb phy probe only once. But if the
usb phy needs to probe twice or more because of some reasons (e.g.
fail to get vbus regulator from RK819), the usb phy 480MHz clk will
be unregistered and registered again, however, the clk framework
doesn't prepare the usb phy 480MHz clk except the first time register
operation. So we move the 480MHz clk register to the end of probe,
and make sure only register it once.
Change-Id: If69378b49035746a7c0107c6a363c4d91dfc15e5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
We need to insert some delay after enabling ADC current
and waiting ADCs are stable for BIST mode mainly.
Change-Id: Ib3cdc6aa36f8674ba8d8defadb47baac72f4745e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
If we playback before capture, the loopback will be
switch to BIST SINE mode by other ADC grps. Let's
fix it.
Change-Id: Ib18a32d87dfed4343edc439bd5c705295eca06f3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Dues to the broken ADC state, it may miss reset ADC digital
register and bring long time (~80ms) unstable and invalid
data at next recording.
Change-Id: Ibf516c054cab99536a4fa3b5fd82f52810352420
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch fixup wrong format if property missing.
Change-Id: I77a86c97b1526fa11a819ad0f2daca803e22ee7f
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
There's an u64 to int convert which may cause overflow.
Change-Id: I7feb46e501828666353506c37a1f35db39ff45f7
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
rkvdec dev status may wrong after irq, this may cause
next frame dec fail. so must add soft reset after irq
Change-Id: I8649206f353f5c3004b09f1255b50258afff1974
Signed-off-by: Siyong Chen <sayon.chen@rock-chips.com>
Cpu clock rate should be less than or equal to low rate when
change pll rate in boost module.
Change-Id: I53c4e66f06bba1e6a85920df0aaceb80176ab016
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
There are some configuration options for cpu boost, such as low
frequency, higt frequency, boost backup pll, and so on.
Change-Id: I35d65f05bbd5ef2a70e4a2e4637e7b4f9f67dda9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add constants and callback functions for the dwmac on rk1808 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Change-Id: I39a75b89cd17331bb4373b9b249ae206e1420e71
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch set attempts to new compatible for thermal founding
on RK1808 SoCs.
Change-Id: I133218cd958e0aabf711a5d22fe5e5da2fbd59ce
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
mkkrnlimg/resource_tool is build from source, don't use $(srctree)
on Makefile.
make modules when $(srctree) == $(objtree) otherwise build will
fail.
Change-Id: I7824d0e9cb60ca40925c4047a203242c6e50505d
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
mkkrnlimg/resource_tool is build from source, don't use $(srctree)
on Makefile.
make modules when $(srctree) == $(objtree) otherwise build will
fail.
Change-Id: If8461a30d450aef089ae7db5f5851d4837e7c303
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
According to "TX/RX Data FIFO Sizes and TX/RX Threshold Control
Register Settings" section in the DWC SuperSpeed USB 3.0 Controller
User Guide, for large latency systems, it may cause unnecessary
performance reduction, and having large TX/RX FIFOs alone is not
sufficient, to solve this issue, the controller provides a packet
threshold feature in the host mode.
For example, on rk3399 platforms, if we set aclk_perilp to 100 MHz,
the system usb bus latency is larger than 2.2 microseconds to access
a 1024-byte packet, to avoid underrun and overrun during the burst,
threshold and burst size control must be set through GTXTHRCFG and
GRXTHRCFG registers.
On rk3399 platforms, only a 4-packet TX FIFO and 3-packet RX FIFO
is implemented due to area constraints, so we can program the USB
Maximum TX Burst Size to 13 and the USB Transmit Packet Count to
4 to avoid TX FIFO underrun during an OUT burst. Similarly, set the
USB Maximum TX Burst Size to 10 and the USB Transmit Packet Count
to 2 to avoid RX FIFO overrrun. To enable the threshold control,
add "snps,gtx-threshold-cfg = <4>, <13>" in dts dwc3 node for Tx,
add "snps,grx-threshold-cfg = <2>, <10>" in dts dwc3 node for Rx.
Change-Id: I7535fe72e6527544a20c5921440b4888e1bada22
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add snps,grx-threshold-cfg and snps,gtx-threshold-cfg properties
which provide values for global Rx/Tx threshold control.
Change-Id: Id470cdc8a1bcf7fe8048ecaa040f5b5662b8ce05
Signed-off-by: William Wu <william.wu@rock-chips.com>
To improve the performance of dual USB transmission.
Change-Id: Ie20d17029e54d299cddadc7a286d9bf6c96b0fbb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Single entry is for target voltage and three entries are for
<target min max> voltages. Change cpu opp-microvolt form one entry to
three entries and set maximum acceptable voltage to a high value so that
regulator device can supply multiple consumers at the same time.
Change-Id: Id74c570afe702e879504a597a3d9fb3754125f2f
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
This patch adds devicetree support to gmac of rk1808 with proper
devicetree compatible strings.
Change-Id: Id35523a10f987cbb9b9c33ad32ab23cb3c6d4e2b
Signed-off-by: David Wu <david.wu@rock-chips.com>
This reverts commit 46d3be8026.
This patch add a new 'regulator-early-min-microvolt' property to limit
the minimal voltage of regulator during kernel startup.
Change-Id: I580f0cceda280b9168e7f489f39785830cd28a28
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This reverts commit a4e0323d13.
If uboot needs a high cpu rate, the voltage should be set to a high
value, and the minimal voltage of regulator will also be set to this
value during kernel startup, so it will be failed to set voltage which
is less than this value when consumers change voltage, for example pvtm.
This patch add a new 'regulator-early-min-microvolt' property to limit
the minimal voltage of regulator during kernel startup and it will no
longer be restricted by uboot.
Change-Id: Ia50920b7627f886fab5c9f65a3fc19946debdff2
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
