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03eca20525
This patch Adds delay after reset deassert to make sure
reset done before do enabling xfer.
Considering the follow situation:
- i2s_mclk for 8K capture [2.048M]
- i2s_hclk for i2s register access [150M]
- pclk_cru for cru register access [100M]
SW HW
i2s reset assert [pclk_cru] |
| |
delay time |
| i2s reset assert [i2s_mclk]
i2s reset deassert [pclk_cru] |
| |
i2s xfer enable [i2s_hclk] |
| i2s reset deassert [i2s_mclk]
Obviously, pclk_cru(10ns per cycle) is much faster than i2s_mclk
(500ns per cycle). so delay should be added after reset deassert
to make sure hw reset done. Otherwise, the race between reset and
enable xfer maybe break i2s data aligned.
Fixes: A 10us delay is enough
SW HW
i2s reset assert [pclk_cru] |
| |
delay 10us |
| i2s reset assert [i2s_mclk]
i2s reset deassert [pclk_cru] |
| |
delay 10us |
| i2s reset deassert [i2s_mclk]
i2s xfer enable [i2s_hclk] |
| |
Change-Id: Id370b0aa13f771053841ce04a554b408e9e3c831
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
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