Files
linux/drivers/clk
Andre Przywara 61b842aaf4 clk: sunxi: A31: Fix wrong AHB gate number
[ Upstream commit ee0b27a3a4 ]

According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-05-15 12:05:24 +09:00
..
2023-05-15 10:39:07 +09:00
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