Leonid Yegoshin 6ebda44f36 MIPS: kernel: {ftrace,kgdb}: Set correct address limit for cache flushes ...

When flushing the icache, make sure the address limit is correct
so the appropriate 'cache' instruction will be used. This has no
impact on cores operating in non-eva mode. However, when EVA is
enabled, we ensure that 'cache' will be used instead of 'cachee'.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

2014-03-26 23:09:18 +01:00

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