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3f4436826e
There is a ASYNC bridge between HCLK and SCLK domain.
On AUPLL case, we found RX data shift ahead 1-Bit on
TRCM-TX sometime (0.00x%), but it success on GPLL(50w+).
The root cause:
HCLK Domain: Config the XFER-3, pull up SIGNAL to HIGH.
SCLK Domain: SCLK_RX/TX samples the HIGH level to start.
Because HCLK Domain is async to SCLK Domain, So, there
is a risk that RX samels the HIGH Level, but RX not.
(at the edge XFER from LOW to HIGH)
Solution:
1, Gate the SCLK
2, Config the XFER-3
3, Ungate the SCLK
Thus, TX/RX Always samples the right Level at the same
time.
After this patch, Test passed over 50w+.
Test Script:
#!/bin/sh
count=0
killall aplay
sleep 1
while true
do
yes `echo -en "\x11\x11\x22\x22"` | tr -d '\n' | \
aplay -D hw:2,0 --period-size=1024 --buffer-size=4096 -r 192000 -c 2 -f s16_le &>/dev/null &
sleep 0.1
rxd=`io -4 0xfe470028 | awk '{print $2}'`
echo "[$count]: $rxd"
if [ "$rxd" != "22221111" ]; then
echo "FAIL: mismatch: $rxd, expected: 22221111"
break
fi
count=$((count + 1))
killall aplay
sleep .1
done
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I10258b92d2f62ab36b5ccc55e8bcc752f3af9d4f
Linux kernel
============
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