Sugar Zhang 42568b67f3 ASoC: rockchip: i2s-tdm: Fix the clk glitch on Calibrate case
BACKGROUND
A short clk giltch (~200us) found on the mclk calibrate case in
kernel 5.10.

  mclk-12.288M - mclk-49.152M (~200us) - mclk-12.288M

The root cause is:

  clk_set_rate(mclk_parent, 49.152M)
  clk_set_rate(mclk, 12.288M)

Prefer to get the mclk rate div from mclk_parent rate, Unfortunately,
the latter will change the mclk_parent rate again in kernel 5.10.

So, do not change mclk parent's rate when it is multiple mclk already,
let clk framework handle it.

e.g.

mclk: clk_i2s1_8ch_tx mclk_parent: clk_i2s_8ch_tx_src

clk_i2s1_8ch_tx_src         0        0        0    12288000
   clk_i2s1_8ch_tx_mux      0        0        0    12288000
      clk_i2s1_8ch_rx       0        0        0    12288000

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ie9e869a48b65e287e60545626e92c9090ab02229
2024-07-23 15:20:51 +08:00
2024-06-17 11:25:35 +08:00
2024-05-08 11:14:32 +08:00
2024-05-08 11:14:32 +08:00
2024-05-08 11:14:32 +08:00
2024-05-08 11:14:32 +08:00
2024-01-25 15:27:52 -08:00

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