Files
linux/drivers
Xing Zheng 913ae6b724 UPSTREAM: clk: rockchip: fix the incorrect pclk_edp div width for RK3399
The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 3e1531dbc3)

Change-Id: Ieffcad3f6d44c71d83b7ed00dd30a4bd45995bb2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2018-07-25 14:43:59 +08:00
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