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9780340751
Set default clock rate and parents for SDHC[0,1,2]. The PLL3 PFD2 maximum frequency is 332Mhz, we can't set it to 389Mhz as USDHC clock parent. Because PLL3 PFD0 is used for NIC, PFD1 is used for audio, the only choice is PFD3 which can reach to 400Mhz. USDHC1 and USDHC2 maximum PCC clock rate is 200Mhz in Over Drive mode, and 100Mhz in Nominal/Low Drive mode, when PTE or PTF is used. The patch adjusts clock parent to PLL3 PFD3 DIV1 for USDHC0, PLL3 PFD3 DIV2 for USDHC1 and USDHC2. And set the max rate to meet restrictions. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.