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c685dba6bd
This soc has two phy's for the pcie one of them using just a different register for settig it up but sharing all the rest of the config. Until now we was presenting this schema as three different phy's in the device tree using the 'phy-cells' node property to discriminate an index and setting up a complete phy for the dual port index. This sometimes worked properly but reconfiguring the same registers twice presents sometimes some unstable pcie links and the ports was not properly being detected. The problems only appears on hard resets and soft resets was properly working. Instead of having this schema just set two phy's in the device ree and use the 'phy-cells' property to say if the port has or not a dual port. Doing this configuration and set up becomes easier, LOC is decreased and the behaviour also gets deterministic with properly and stable pcie links in both hard and soft resets. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.