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AMD uses the cache l3 boundary for schemata masks. Update it accordigly. Signed-off-by: Babu Moger <babu.moger@amd.com> Co-developed-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
15 KiB
15 KiB