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d3a51507e4
The flexcan IP core has up to 64 mailboxes, each one has a corresponding interrupt bit in the iflag1 or iflag2 registers and a mask bit in the imask1 or imask2 registers. In the timestamp (i.e. non FIFO) mode the driver needs to mask all non RX interrupt sources, it uses the precomputed value rx_mask of struct flexcan_priv for this. In certain use cases, for example the CANFD mode, the contents of the iflag2 register is completely masked. This patch optimizes the flexcan_read_reg_iflag_rx() function by not reading the iflag1 or iflag2 register if the contents is masked. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.