According to "TX/RX Data FIFO Sizes and TX/RX Threshold Control
Register Settings" section in the DWC SuperSpeed USB 3.0 Controller
User Guide, for large latency systems, it may cause unnecessary
performance reduction, and having large TX/RX FIFOs alone is not
sufficient, to solve this issue, the controller provides a packet
threshold feature in the host mode.
For example, on rk3399 platforms, if we set aclk_perilp to 100 MHz,
the system usb bus latency is larger than 2.2 microseconds to access
a 1024-byte packet, to avoid underrun and overrun during the burst,
threshold and burst size control must be set through GTXTHRCFG and
GRXTHRCFG registers.
On rk3399 platforms, only a 4-packet TX FIFO and 3-packet RX FIFO
is implemented due to area constraints, so we can program the USB
Maximum TX Burst Size to 13 and the USB Transmit Packet Count to
4 to avoid TX FIFO underrun during an OUT burst. Similarly, set the
USB Maximum TX Burst Size to 10 and the USB Transmit Packet Count
to 2 to avoid RX FIFO overrrun. To enable the threshold control,
add "snps,gtx-threshold-cfg = <4>, <13>" in dts dwc3 node for Tx,
add "snps,grx-threshold-cfg = <2>, <10>" in dts dwc3 node for Rx.
Change-Id: I7535fe72e6527544a20c5921440b4888e1bada22
Signed-off-by: William Wu <william.wu@rock-chips.com>
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