Files
linux/drivers
Shawn Lin c420c1e4db FROMLIST: clk: rockchip: Prevent calculating mmc phase if clock rate is zero
The MMC sample and drv clock for rockchip platforms are derived from
the bus clock output to the MMC/SDIO card. So it should never happens
that the clk rate is zero given it should inherits the clock rate from
its parent. If something goes wrong and makes the clock rate to be zero,
the calculation would be wrong but may still make the mmc tuning process
work luckily. However it makes people harder to debug when the following
data transfer is unstable.

Change-Id: Ifeb4c063cb73e0a444fd8819ef3128256331cd7a
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from https://patchwork.kernel.org/patch/10258071/)
2018-03-09 14:07:09 +08:00
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