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The Lantiq VRX200 SoCs embed a PCIe PHY in the "sram" bus. Unlike most other IP blocks on this SoC the register values are only 16-bit wide. Like other IP blocks on this SoC the register values are in big endian. The PHY embeds a PLL which can be configured in various modes. Only the 36MHz mode is supported for now, the other modes can be implemented when there's a board which actually needs them. OpenWrt uses the out-of-tree vendor driver and all supported boards there only need the 36MHz mode. There are two input clocks: - the "pdi" clock enables the register access - the "phy" clock is the clock input and enables the internal PLL There are two reset lines: - "phy" resets the PHY itself - the "pcie" reset line is shared between the PHY and the PCIe controller While the VRX200 SoC has only one PCIe controller and PHY the ARX300 uses two identical PCIe controllers and PHYs which are compatible with the PCIe controller and PHY on VRX200. Add a driver for this PHY so PCIe support can be enabled on these SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.