Kuppuswamy Sathyanarayanan e6749c89b4 platform/x86: intel_pmc_ipc: fix gcr offset
According to Broxton APL spec, PMC MIMO resources for Global Control
Registers(GCR) are located at 4K(0x1000) offset from IPC base address.
In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR
region base address from IPC base address and its current value of
0x1008 is incorrect because it points to location for PMC_CFG register
and not the GCR base address itself.

GCR Base = IPC1 Base + 0x1000.

This patch fixes this offset issue.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-04-28 21:51:26 +03:00
2017-04-17 15:30:28 -07:00
2017-04-17 15:30:28 -07:00
2017-02-13 12:24:56 -05:00
2016-05-23 17:04:14 -07:00
2017-03-19 19:09:39 -07:00

Linux kernel
============

This file was moved to Documentation/admin-guide/README.rst

Please notice that there are several guides for kernel developers and users.
These guides can be rendered in a number of formats, like HTML and PDF.

In order to build the documentation, use ``make htmldocs`` or
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There are various text files in the Documentation/ subdirectory,
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See Documentation/00-INDEX for a list of what is contained in each file.

Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.
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