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The AD7768-1 core ADC receives a master clock signal (MCLK). The MCLK frequency combined with the MCLK division and the digital filter decimation rates, determines the sampling frequency. Along with MCLK_DIV, the power mode is also configured according to datasheet recommendations. From user space, available sampling frequencies can be read. However, it is not required for an exact value to be entered, since the driver will look for the closest available match. When the device configuration changes (for example, if the filter decimation rate changes), a SYNC_IN pulse is required. Signed-off-by: Stefan Popa <stefan.popa@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.