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hdmirx: trim value err when resume [1/1]

Browse Source 
PD#SWPL-147482

Problem:
trim value err when resume.

Solution:
store default value when probe.

Verify:
txhd2

Change-Id: Ic11b359d8ab8835e6de0e31833840cf399329e4c
Signed-off-by: yaoyu.xu <yaoyu.xu@amlogic.com>
This commit is contained in:
yaoyu.xu
2023-11-24 16:53:21 +08:00
committed by Luan Yuan
parent 91b9f67b1a
commit 02fba23c98
8 changed files with 35 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.c
+2 -1
View File
@@ -206,7 +206,7 @@ int disable_hdr;
int vrr_range_dynamic_update_en;
int allm_update_en;
int rx_phy_level = 1;
int def_trim_value;
static struct notifier_block aml_hdcp22_pm_notifier = {
.notifier_call = aml_hdcp22_pm_notify,
};
@@ -3925,6 +3925,7 @@ static int hdmirx_probe(struct platform_device *pdev)
if (rx_info.chip_id >= CHIP_ID_T3X)
rx_emp1_resource_allocate(&pdev->dev);
//rx[rx_info.main_port].port = rx[rx_info.main_port].arc_port;
def_trim_value = aml_phy_get_def_trim_value();
aml_phy_get_trim_val();
edid_auto_mode_init();
hdmirx_hw_probe();
drivers/media/vin/tvin/hdmirx/hdmi_rx_drv.h
+3 -1
View File
@@ -145,7 +145,8 @@
/* 2023 09 27 reduce phy power */
/* optimize afifo configuration */
/* 2023.11.03 disable DDR access when suspend */
#define RX_VER2 "ver.2023/11/03"
/* 2023.12.1 fix trim value err when resume */
#define RX_VER2 "ver.2023/12/01"
#define PFIFO_SIZE 160
#define HDCP14_KEY_SIZE 368
@@ -1033,6 +1034,7 @@ extern char edid_cur[EDID_SIZE];
extern int vpp_mute_cnt;
extern int gcp_mute_cnt;
extern int gcp_mute_flag[4];
extern int def_trim_value;
#ifdef CONFIG_AMLOGIC_MEDIA_VRR
extern struct notifier_block vrr_notify;
#endif
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+21 -1
View File
@@ -6147,7 +6147,7 @@ bool is_ft_trim_done(void)
/*T5 todo:*/
void aml_phy_get_trim_val_tl1_tm2(void)
{
phy_trim_val = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1);
phy_trim_val = def_trim_value;
dts_debug_flag = (phy_term_lel >> 4) & 0x1;
rlevel = phy_term_lel & 0xf;
if (rlevel > 11)
@@ -7338,3 +7338,23 @@ void reset_pcs(u8 port)
hdmirx_wr_top(TOP_SW_RESET, 0, port);
}
int aml_phy_get_def_trim_value(void)
{
// t3x to do
if (rx_info.chip_id >= CHIP_ID_TL1 &&
rx_info.chip_id <= CHIP_ID_TM2)
return rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1);
else if (rx_info.chip_id >= CHIP_ID_T5 &&
rx_info.chip_id <= CHIP_ID_T5D)
return hdmirx_rd_amlphy(T5_HHI_RX_PHY_MISC_CNTL1);
else if (rx_info.chip_id >= CHIP_ID_T7 &&
rx_info.chip_id <= CHIP_ID_T5W)
return hdmirx_rd_amlphy(T7_HHI_RX_PHY_MISC_CNTL1);
else if (rx_info.chip_id == CHIP_ID_T5M)
return hdmirx_rd_amlphy(T5M_HDMIRX20PHY_DCHA_MISC1);
else if (rx_info.chip_id == CHIP_ID_TXHD2)
return hdmirx_rd_amlphy(TXHD2_HDMIRX20PHY_DCHA_MISC1);
else
return 0;
}
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw.h
+1
View File
@@ -3474,6 +3474,7 @@ void rx_set_color_bar(bool en, unsigned int lvl, u8 port);
void reset_pcs(u8 port);
bool is_earc_hpd_low(void);
void rx_mute_vpp(u8 port);
int aml_phy_get_def_trim_value(void);
/* t3x */
void hdmi_tx_rx_frl_training_main(u8 port);
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t5.c
+1 -1
View File
@@ -869,7 +869,7 @@ void aml_phy_get_trim_val_t5(void)
dts_debug_flag = (phy_term_lel >> 4) & 0x1;
if (dts_debug_flag == 0) {
data32 = hdmirx_rd_amlphy(T5_HHI_RX_PHY_MISC_CNTL1);
data32 = def_trim_value;
rterm_trim_val_t5 = (data32 >> 12) & 0xf;
rterm_trim_flag_t5 = data32 & 0x1;
} else {
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t5m.c
+3 -3
View File
@@ -645,7 +645,7 @@ void aml_phy_offset_cal_t5m(void)
data32 = 0xffe00100;
if (rterm_trim_flag_t5m) {
data32 = ((data32 & (~((0xf << 12) | 0x1))) |
(rterm_trim_val_t5m << 12) | rterm_trim_flag_t5m);
(rterm_trim_val_t5m << 12) | rterm_trim_flag_t5m << 4);
}
hdmirx_wr_amlphy(T5M_HDMIRX20PHY_DCHA_MISC1, data32);
usleep_range(10, 20);
@@ -1285,7 +1285,7 @@ void aml_phy_get_trim_val_t5m(void)
dts_debug_flag = (phy_term_lel >> 4) & 0x1;
if (dts_debug_flag == 0) {
data32 = hdmirx_rd_amlphy(T5M_HDMIRX20PHY_DCHA_MISC1);
data32 = def_trim_value;
rterm_trim_val_t5m = (data32 >> 12) & 0xf;
rterm_trim_flag_t5m = data32 & 0x1;
} else {
@@ -1349,7 +1349,7 @@ void aml_phy_cfg_t5m(void)
if (dts_debug_flag)
rterm_trim_val_t5m = t5m_rlevel[rlevel];
data32 = ((data32 & (~((0xf << 12) | 0x1))) |
(rterm_trim_val_t5m << 12) | rterm_trim_flag_t5m);
(rterm_trim_val_t5m << 12) | rterm_trim_flag_t5m << 4);
}
hdmirx_wr_amlphy(T5M_HDMIRX20PHY_DCHA_MISC1, data32);
usleep_range(5, 10);
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_t7.c
+1 -1
View File
@@ -913,7 +913,7 @@ void aml_phy_get_trim_val_t7(void)
dts_debug_flag = (phy_term_lel >> 4) & 0x1;
if (dts_debug_flag == 0) {
data32 = hdmirx_rd_amlphy(T7_HHI_RX_PHY_MISC_CNTL1);
data32 = def_trim_value;
rterm_trim_val_t7 = (data32 >> 12) & 0xf;
rterm_trim_flag_t7 = data32 & 0x1;
} else {
drivers/media/vin/tvin/hdmirx/hdmi_rx_hw_txhd2.c
+3 -3
View File
@@ -646,7 +646,7 @@ void aml_phy_offset_cal_txhd2(void)
data32 = 0xffe00100;
if (rterm_trim_flag_txhd2) {
data32 = ((data32 & (~((0xf << 12) | 0x1))) |
(rterm_trim_val_txhd2 << 12) | rterm_trim_flag_txhd2);
(rterm_trim_val_txhd2 << 12) | rterm_trim_flag_txhd2 << 4);
}
hdmirx_wr_amlphy(TXHD2_HDMIRX20PHY_DCHA_MISC1, data32);
usleep_range(10, 20);
@@ -1337,7 +1337,7 @@ void aml_phy_get_trim_val_txhd2(void)
dts_debug_flag = (phy_term_lel >> 4) & 0x1;
if (dts_debug_flag == 0) {
data32 = hdmirx_rd_amlphy(TXHD2_HDMIRX20PHY_DCHA_MISC1);
data32 = def_trim_value;
rterm_trim_val_txhd2 = (data32 >> 12) & 0xf;
rterm_trim_flag_txhd2 = data32 & 0x1;
} else {
@@ -1401,7 +1401,7 @@ void aml_phy_cfg_txhd2(void)
if (dts_debug_flag)
rterm_trim_val_txhd2 = txhd2_rlevel[rlevel];
data32 = ((data32 & (~((0xf << 12) | 0x1))) |
(rterm_trim_val_txhd2 << 12) | rterm_trim_flag_txhd2);
(rterm_trim_val_txhd2 << 12) | rterm_trim_flag_txhd2 << 4);
}
hdmirx_wr_amlphy(TXHD2_HDMIRX20PHY_DCHA_MISC1, data32);
usleep_range(5, 10);