mirror of
https://github.com/hardkernel/kernel_common_drivers.git
synced 2026-06-25 12:03:48 +09:00
dts: add t3x device tree [1/1]
PD#SWPL-110944 Problem: t3x bringup Solution: add t3x device tree Verify: t3x z1 Change-Id: I30365c1a1caafca531c2176070cb447b751d5a2f Signed-off-by: Jian Hu <jian.hu@amlogic.com>
This commit is contained in:
Jian Hu
@@ -59,3 +59,4 @@ dtb-y += t5w_t962d4_at301_1.5g.dtb
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dtb-y += t5w_t962d4_at301_R.dtb
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dtb-y += t5w_t962d4_at301_1g_R.dtb
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dtb-y += t5w_t962d4_at301_1.5g_R.dtb
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dtb-y += t3x_pxp.dtb
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,227 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/display/meson-drm-ids.h>
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#include "mesont3x.dtsi"
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/ {
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drm_amcvbsout: drm-amcvbsout {
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status = "disabled";
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compatible = "amlogic, drm-cvbsout";
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dev_name = "meson-amcvbsout";
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ports {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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cvbs_to_drm: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drm_to_cvbs>;
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};
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};
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};
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};
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drm_vpu: drm-vpu@0xff800000 {
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status = "disabled";
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compatible = "amlogic, meson-s5-vpu";
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memory-region = <&logo_reserved>;
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osd_ver = /bits/ 8 <OSD_V7>;
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reg = <0x0 0xff800000 0x0 0x40000>;
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reg-names = "vcbus";
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interrupts = <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "viu-vsync", "viu2-vsync";
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dma-coherent;
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/*EXTERNAL port for driver outside of drm.*/
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connectors_dev: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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drm_to_hdmitx: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&hdmitx_to_drm>;
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};
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drm_to_cvbs: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&cvbs_to_drm>;
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};
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};
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};
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drm_subsystem: drm-subsystem {
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status = "okay";
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compatible = "amlogic, drm-subsystem";
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vpu_dma_mask = <1>; /* 0: <= 4G, 1: > 4G */
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ports = <&connectors_dev>;
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fbdev_sizes = <1920 1080 1920 2160 32>;
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max_fb_size = <1>; /** 0:1080p fb 1:4k fb */
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max_sizes = <8192 8192>;
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osd_ver = /bits/ 8 <OSD_V7>;
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vfm_mode = <1>; /** 0:drm mode 1:composer mode */
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memory-region = <&logo_reserved>;
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crtc_masks = <3 7 1>; /*for encoder: 0:hdmi 1:lcd 2:cvbs*/
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crtcmask_of_osd = <0 0 1 2>; /* indicate the crtc mask of osd plane */
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crtcmask_of_video = <0 1 2>; /* indicate the crtc mask of video plane */
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logo_skip = <0>;
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vpu_topology: vpu_topology {
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vpu_blocks {
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osd1_block: block@0 {
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id = /bits/ 8 <OSD1_BLOCK>;
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index = /bits/ 8 <0>;
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type = /bits/ 8 <0>;
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block_name = "osd1_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &afbc1_block>;
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};
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osd3_block: block@1 {
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id = /bits/ 8 <OSD3_BLOCK>;
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index = /bits/ 8 <2>;
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type = /bits/ 8 <0>;
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block_name = "osd3_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &afbc2_block>;
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};
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afbc1_block: block@2 {
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id = /bits/ 8 <AFBC1_BLOCK>;
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index = /bits/ 8 <0>;
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type = /bits/ 8 <1>;
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block_name = "afbc1_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &osd1_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &scaler1_block>;
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};
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afbc2_block: block@3 {
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id = /bits/ 8 <AFBC2_BLOCK>;
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index = /bits/ 8 <1>;
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type = /bits/ 8 <1>;
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block_name = "afbc2_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &osd3_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &scaler3_block>;
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};
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scaler1_block: block@4 {
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id = /bits/ 8 <SCALER1_BLOCK>;
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index = /bits/ 8 <0>;
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type = /bits/ 8 <2>;
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block_name = "scaler1_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &afbc1_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &hdr1_block>;
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};
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scaler3_block: block@5 {
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id = /bits/ 8 <SCALER3_BLOCK>;
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index = /bits/ 8 <2>;
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type = /bits/ 8 <2>;
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block_name = "scaler3_block";
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &afbc2_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &hdr3_block>;
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};
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hdr1_block: block@6 {
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id = /bits/ 8 <HDR1_BLOCK>;
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index = /bits/ 8 <0>;
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block_name = "hdr1_block";
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type = /bits/ 8 <4>;
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &scaler1_block>;
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num_out_links = /bits/ 8 <0x3>;
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out_links = <0 &slice2ppc_block>,
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<1 &osd_blend_block>,
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<0 &vpp_postblend_block>;
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};
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hdr3_block: block@7 {
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id = /bits/ 8 <HDR3_BLOCK>;
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index = /bits/ 8 <2>;
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block_name = "hdr3_block";
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type = /bits/ 8 <4>;
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num_in_links = /bits/ 8 <0x1>;
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in_links = <0 &scaler3_block>;
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num_out_links = /bits/ 8 <0x3>;
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out_links = <1 &slice2ppc_block>,
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<3 &osd_blend_block>,
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<0 &vpp_postblend_block>;
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};
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slice2ppc_block: block@8 {
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id = /bits/ 8 <SLICE2PPC_BLOCK>;
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index = /bits/ 8 <0>;
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block_name = "slice2ppc_block";
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type = /bits/ 8 <8>;
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num_in_links = /bits/ 8 <0x2>;
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in_links = <1 &hdr1_block>,
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<1 &hdr3_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &osd_blend_block>;
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};
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osd_blend_block: block@9 {
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id = /bits/ 8 <OSD_BLEND_BLOCK>;
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block_name = "osd_blend_block";
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type = /bits/ 8 <3>;
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num_in_links = /bits/ 8 <0x3>;
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in_links = <0 &slice2ppc_block>,
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<0 &hdr1_block>,
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<0 &hdr3_block>;
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num_out_links = /bits/ 8 <0x1>;
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out_links = <0 &vpp_postblend_block>;
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};
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vpp_postblend_block: block@10 {
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id = /bits/ 8 <VPP_POSTBLEND_BLOCK>;
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index = /bits/ 8 <0>;
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block_name = "vpp_postblend_block";
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type = /bits/ 8 <6>;
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num_in_links = /bits/ 8 <0x3>;
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in_links = <0 &hdr1_block>,
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<0 &hdr3_block>,
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<0 &osd_blend_block>;
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num_out_links = <0x0>;
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};
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video1_block: block@11 {
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id = /bits/ 8 <VIDEO1_BLOCK>;
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index = /bits/ 8 <0>;
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type = /bits/ 8 <7>;
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block_name = "video1_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x0>;
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};
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video2_block: block@12 {
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id = /bits/ 8 <VIDEO2_BLOCK>;
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index = /bits/ 8 <1>;
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type = /bits/ 8 <7>;
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block_name = "video2_block";
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num_in_links = /bits/ 8 <0x0>;
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num_out_links = /bits/ 8 <0x0>;
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};
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};
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};
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vpu_hw_para: vpu_hw_para@0 {
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osd_ver = /bits/ 8 <OSD_V7>;
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afbc_type = /bits/ 8 <0x2>;
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has_deband = /bits/ 8 <0x1>;
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has_lut = /bits/ 8 <0x1>;
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has_rdma = /bits/ 8 <0x1>;
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osd_fifo_len = /bits/ 8 <64>;
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vpp_fifo_len = /bits/ 32 <0xfff>;
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};
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};
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};
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&amhdmitx {
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ports {
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmitx_to_drm: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drm_to_hdmitx>;
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};
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};
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};
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};
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,92 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __S5_AUDIO_CLK_H__
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#define __S5_AUDIO_CLK_H__
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/*
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* CLKID audio index values
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*/
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#define CLKID_AUDIO_GATE_DDR_ARB 0
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#define CLKID_AUDIO_GATE_PDM 1
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#define CLKID_AUDIO_GATE_TDMINA 2
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#define CLKID_AUDIO_GATE_TDMINB 3
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#define CLKID_AUDIO_GATE_TDMINC 4
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#define CLKID_AUDIO_GATE_TDMINLB 5
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#define CLKID_AUDIO_GATE_TDMOUTA 6
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#define CLKID_AUDIO_GATE_TDMOUTB 7
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#define CLKID_AUDIO_GATE_TDMOUTC 8
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#define CLKID_AUDIO_GATE_FRDDRA 9
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#define CLKID_AUDIO_GATE_FRDDRB 10
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#define CLKID_AUDIO_GATE_FRDDRC 11
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#define CLKID_AUDIO_GATE_TODDRA 12
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#define CLKID_AUDIO_GATE_TODDRB 13
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#define CLKID_AUDIO_GATE_TODDRC 14
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#define CLKID_AUDIO_GATE_LOOPBACKA 15
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#define CLKID_AUDIO_GATE_SPDIFIN 16
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#define CLKID_AUDIO_GATE_SPDIFOUT_A 17
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#define CLKID_AUDIO_GATE_RESAMPLEA 18
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#define CLKID_AUDIO_GATE_RESERVED0 19
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#define CLKID_AUDIO_GATE_RESERVED1 20
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#define CLKID_AUDIO_GATE_SPDIFOUT_B 21
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#define CLKID_AUDIO_GATE_EQDRC 22
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#define CLKID_AUDIO_GATE_RESERVED2 23
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#define CLKID_AUDIO_GATE_RESERVED3 24
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#define CLKID_AUDIO_GATE_RESERVED4 25
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#define CLKID_AUDIO_GATE_RESAMPLEB 26
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#define CLKID_AUDIO_GATE_TOVAD 27
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#define CLKID_AUDIO_GATE_AUDIOLOCKER 28
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#define CLKID_AUDIO_GATE_SPDIFIN_LB 29
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#define CLKID_AUDIO_GATE_FRATV 30
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#define CLKID_AUDIO_GATE_FRHDMIRX 31
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/* Gate En1 */
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#define CLKID_AUDIO_GATE_FRDDRD 32
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#define CLKID_AUDIO_GATE_TODDRD 33
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#define CLKID_AUDIO_GATE_LOOPBACKB 34
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#define CLKID_AUDIO_GATE_FRDDRE 35
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#define CLKID_AUDIO_GATE_EARCRX 36
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#define CLKID_AUDIO_GATE_TDMIND 37
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#define CLKID_AUDIO_GATE_TDMOUTD 38
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#define CLKID_AUDIO_GATE_PCPD_A 39
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#define CLKID_AUDIO_GATE_PCPD_B 40
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#define CLKID_AUDIO_GATE_MAX 41
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#define MCLK_BASE CLKID_AUDIO_GATE_MAX
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#define CLKID_AUDIO_MCLK_A (MCLK_BASE + 0)
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#define CLKID_AUDIO_MCLK_B (MCLK_BASE + 1)
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#define CLKID_AUDIO_MCLK_C (MCLK_BASE + 2)
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#define CLKID_AUDIO_MCLK_D (MCLK_BASE + 3)
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#define CLKID_AUDIO_MCLK_E (MCLK_BASE + 4)
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#define CLKID_AUDIO_MCLK_F (MCLK_BASE + 5)
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#define CLKID_AUDIO_SPDIFIN (MCLK_BASE + 6)
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#define CLKID_AUDIO_SPDIFOUT_A (MCLK_BASE + 7)
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#define CLKID_AUDIO_RESAMPLE_A (MCLK_BASE + 8)
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#define CLKID_AUDIO_LOCKER_OUT (MCLK_BASE + 9)
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#define CLKID_AUDIO_LOCKER_IN (MCLK_BASE + 10)
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#define CLKID_AUDIO_PDMIN0 (MCLK_BASE + 11)
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#define CLKID_AUDIO_PDMIN1 (MCLK_BASE + 12)
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#define CLKID_AUDIO_SPDIFOUT_B (MCLK_BASE + 13)
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#define CLKID_AUDIO_RESAMPLE_B (MCLK_BASE + 14)
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#define CLKID_AUDIO_SPDIFIN_LB (MCLK_BASE + 15)
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#define CLKID_AUDIO_EQDRC (MCLK_BASE + 16)
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#define CLKID_AUDIO_VAD (MCLK_BASE + 17)
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#define CLKID_EARCTX_CMDC (MCLK_BASE + 18)
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#define CLKID_EARCTX_DMAC (MCLK_BASE + 19)
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#define CLKID_EARCRX_CMDC (MCLK_BASE + 20)
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#define CLKID_EARCRX_DMAC (MCLK_BASE + 21)
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#define CLKID_AUDIO_MCLK_PAD0 (MCLK_BASE + 22)
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#define CLKID_AUDIO_MCLK_PAD1 (MCLK_BASE + 23)
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#define CLKID_AUDIO_MCLK_PAD2 (MCLK_BASE + 24)
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#define CLKID_AUDIO_MCLK_PAD3 (MCLK_BASE + 25)
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#define CLKID_AUDIO_PDMBIN0 (MCLK_BASE + 26)
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#define CLKID_AUDIO_PDMBIN1 (MCLK_BASE + 27)
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#define NUM_AUDIO_CLKS (MCLK_BASE + 28)
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#endif /* __S5_AUDIO_CLK_H__ */
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@@ -0,0 +1,408 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
*/
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||||
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#ifndef __S5_CLKC_H
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#define __S5_CLKC_H
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/*
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* CLKID index values
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*/
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||||
#define CLKID_SYS_PLL_DCO 0
|
||||
#define CLKID_SYS_PLL 1
|
||||
#define CLKID_SYS1_PLL_DCO 2
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||||
#define CLKID_SYS1_PLL 3
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#define CLKID_FIXED_PLL_DCO 4
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#define CLKID_FIXED_PLL 5
|
||||
#define CLKID_FCLK_DIV2_DIV 6
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#define CLKID_FCLK_DIV2 7
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#define CLKID_FCLK_DIV3_DIV 8
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||||
#define CLKID_FCLK_DIV3 9
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||||
#define CLKID_FCLK_DIV4_DIV 10
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||||
#define CLKID_FCLK_DIV4 11
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||||
#define CLKID_FCLK_DIV5_DIV 12
|
||||
#define CLKID_FCLK_DIV5 13
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||||
#define CLKID_FCLK_DIV7_DIV 14
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||||
#define CLKID_FCLK_DIV7 15
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#define CLKID_FCLK_DIV2P5_DIV 16
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||||
#define CLKID_FCLK_DIV2P5 17
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||||
#define CLKID_FCLK_CLK50M_DIV 18
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||||
#define CLKID_FCLK_CLK50M 19
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||||
#define CLKID_GP0_PLL_DCO 20
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||||
#define CLKID_GP0_PLL 21
|
||||
#define CLKID_GP1_PLL_DCO 22
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||||
#define CLKID_GP1_PLL 23
|
||||
#define CLKID_CPU_DYN_CLK 24
|
||||
#define CLKID_CPU_CLK 25
|
||||
#define CLKID_HIFI_PLL_DCO 26
|
||||
#define CLKID_HIFI_PLL 27
|
||||
#define CLKID_PCIE_PLL_DCO 28
|
||||
#define CLKID_PCIE_PLL_DCO_DIV2 29
|
||||
#define CLKID_PCIE_PLL_OD 30
|
||||
#define CLKID_PCIE_PLL 31
|
||||
#define CLKID_PCIE_BGP 32
|
||||
#define CLKID_PCIE_HCSL_OUT 33
|
||||
#define CLKID_PCIE_HCSL_PAD 34
|
||||
#define CLKID_PCIE_HCSL_IN_PAD 35
|
||||
#define CLKID_PCIE_CLK_IN 36
|
||||
#define CLKID_PCIE1_PLL_DCO 37
|
||||
#define CLKID_PCIE1_PLL_DCO_DIV2 38
|
||||
#define CLKID_PCIE1_PLL_OD 39
|
||||
#define CLKID_PCIE1_PLL 40
|
||||
#define CLKID_PCIE1_BGP 41
|
||||
#define CLKID_PCIE1_HCSL_OUT 42
|
||||
#define CLKID_PCIE1_HCSL_PAD 43
|
||||
#define CLKID_PCIE1_HCSL_IN_PAD 44
|
||||
#define CLKID_PCIE1_CLK_IN 45
|
||||
#define CLKID_SYS2_PLL_DCO 46
|
||||
#define CLKID_SYS2_PLL 47
|
||||
#define CLKID_A76_DYN_CLK 48
|
||||
#define CLKID_A76_CLK 49
|
||||
#define CLKID_DSU_DYN_CLK 50
|
||||
#define CLKID_DSU_CLK 51
|
||||
#define CLKID_DSU_FINAL_CLK 52
|
||||
#define CLKID_GP2_PLL_DCO 53
|
||||
#define CLKID_GP2_PLL 54
|
||||
#define CLKID_NNA_PLL_DCO 55
|
||||
#define CLKID_NNA_PLL 56
|
||||
#define CLKID_NNA_PLL_AUDIO 57
|
||||
#define CLKID_HIFI1_PLL_DCO 58
|
||||
#define CLKID_HIFI1_PLL 59
|
||||
#define CLKID_FDLE_PLL_DCO 60
|
||||
#define CLKID_FDLE_PLL_OD 61
|
||||
#define CLKID_FDLE_PLL_OD1 62
|
||||
#define CLKID_FDLE_PLL_TMDS 63
|
||||
#define CLKID_FDLE_PLL_PIXEL 64
|
||||
#define CLKID_CPU4_CLK 65
|
||||
|
||||
#define CLKID_BASE 66
|
||||
#define CLKID_RTC_32K_CLKIN (CLKID_BASE + 0)
|
||||
#define CLKID_RTC_32K_DIV (CLKID_BASE + 1)
|
||||
#define CLKID_RTC_32K_XATL (CLKID_BASE + 2)
|
||||
#define CLKID_RTC_32K_SEL (CLKID_BASE + 3)
|
||||
#define CLKID_RTC_CLK (CLKID_BASE + 4)
|
||||
#define CLKID_SYS_CLK_1_SEL (CLKID_BASE + 5)
|
||||
#define CLKID_SYS_CLK_1_DIV (CLKID_BASE + 6)
|
||||
#define CLKID_SYS_CLK_1 (CLKID_BASE + 7)
|
||||
#define CLKID_SYS_CLK_0_SEL (CLKID_BASE + 8)
|
||||
#define CLKID_SYS_CLK_0_DIV (CLKID_BASE + 9)
|
||||
#define CLKID_SYS_CLK_0 (CLKID_BASE + 10)
|
||||
#define CLKID_SYS_CLK (CLKID_BASE + 11)
|
||||
#define CLKID_CECA_32K_CLKIN (CLKID_BASE + 12)
|
||||
#define CLKID_CECA_32K_DIV (CLKID_BASE + 13)
|
||||
#define CLKID_CECA_32K_MUX_PRE (CLKID_BASE + 14)
|
||||
#define CLKID_CECA_32K_MUX (CLKID_BASE + 15)
|
||||
#define CLKID_CECA_32K_CLKOUT (CLKID_BASE + 16)
|
||||
#define CLKID_CECB_32K_CLKIN (CLKID_BASE + 17)
|
||||
#define CLKID_CECB_32K_DIV (CLKID_BASE + 18)
|
||||
#define CLKID_CECB_32K_MUX_PRE (CLKID_BASE + 19)
|
||||
#define CLKID_CECB_32K_MUX (CLKID_BASE + 20)
|
||||
#define CLKID_CECB_32K_CLKOUT (CLKID_BASE + 21)
|
||||
#define CLKID_AXICLK_1_SEL (CLKID_BASE + 22)
|
||||
#define CLKID_AXICLK_1_DIV (CLKID_BASE + 23)
|
||||
#define CLKID_AXICLK_1 (CLKID_BASE + 24)
|
||||
#define CLKID_AXICLK_0_SEL (CLKID_BASE + 25)
|
||||
#define CLKID_AXICLK_0_DIV (CLKID_BASE + 26)
|
||||
#define CLKID_AXICLK_0 (CLKID_BASE + 27)
|
||||
#define CLKID_AXICLK (CLKID_BASE + 28)
|
||||
#define CLKID_24M_CLK_GATE (CLKID_BASE + 29)
|
||||
#define CLKID_24M_DIV2 (CLKID_BASE + 30)
|
||||
#define CLKID_12M_CLK (CLKID_BASE + 31)
|
||||
#define CLKID_25M_CLK_DIV (CLKID_BASE + 32)
|
||||
#define CLKID_25M_CLK (CLKID_BASE + 33)
|
||||
|
||||
#define VIDEO_BASE (CLKID_BASE + 34)
|
||||
#define CLKID_VCLK_SEL (VIDEO_BASE + 0)
|
||||
#define CLKID_VCLK2_SEL (VIDEO_BASE + 1)
|
||||
#define CLKID_VCLK_INPUT (VIDEO_BASE + 2)
|
||||
#define CLKID_VCLK2_INPUT (VIDEO_BASE + 3)
|
||||
#define CLKID_VCLK_DIV (VIDEO_BASE + 4)
|
||||
#define CLKID_VCLK2_DIV (VIDEO_BASE + 5)
|
||||
#define CLKID_VCLK (VIDEO_BASE + 6)
|
||||
#define CLKID_VCLK2 (VIDEO_BASE + 7)
|
||||
#define CLKID_VCLK_DIV1 (VIDEO_BASE + 8)
|
||||
#define CLKID_VCLK_DIV2_EN (VIDEO_BASE + 9)
|
||||
#define CLKID_VCLK_DIV4_EN (VIDEO_BASE + 10)
|
||||
#define CLKID_VCLK_DIV6_EN (VIDEO_BASE + 11)
|
||||
#define CLKID_VCLK_DIV12_EN (VIDEO_BASE + 12)
|
||||
#define CLKID_VCLK2_DIV1 (VIDEO_BASE + 13)
|
||||
#define CLKID_VCLK2_DIV2_EN (VIDEO_BASE + 14)
|
||||
#define CLKID_VCLK2_DIV4_EN (VIDEO_BASE + 15)
|
||||
#define CLKID_VCLK2_DIV6_EN (VIDEO_BASE + 16)
|
||||
#define CLKID_VCLK2_DIV12_EN (VIDEO_BASE + 17)
|
||||
#define CLKID_VCLK_DIV2 (VIDEO_BASE + 18)
|
||||
#define CLKID_VCLK_DIV4 (VIDEO_BASE + 19)
|
||||
#define CLKID_VCLK_DIV6 (VIDEO_BASE + 20)
|
||||
#define CLKID_VCLK_DIV12 (VIDEO_BASE + 21)
|
||||
#define CLKID_VCLK2_DIV2 (VIDEO_BASE + 22)
|
||||
#define CLKID_VCLK2_DIV4 (VIDEO_BASE + 23)
|
||||
#define CLKID_VCLK2_DIV6 (VIDEO_BASE + 24)
|
||||
#define CLKID_VCLK2_DIV12 (VIDEO_BASE + 25)
|
||||
#define CLKID_CTS_ENCI_SEL (VIDEO_BASE + 26)
|
||||
#define CLKID_CTS_ENCT_SEL (VIDEO_BASE + 28)
|
||||
#define CLKID_CTS_ENCP_SEL (VIDEO_BASE + 29)
|
||||
#define CLKID_CTS_ENCL_SEL (VIDEO_BASE + 30)
|
||||
#define CLKID_CTS_VDAC_SEL (VIDEO_BASE + 31)
|
||||
#define CLKID_CTS_ENCI (VIDEO_BASE + 32)
|
||||
#define CLKID_CTS_ENCT (VIDEO_BASE + 33)
|
||||
#define CLKID_CTS_ENCP (VIDEO_BASE + 34)
|
||||
#define CLKID_CTS_ENCL (VIDEO_BASE + 35)
|
||||
#define CLKID_CTS_VDAC (VIDEO_BASE + 36)
|
||||
|
||||
#define PERI_BASE (VIDEO_BASE + 37)
|
||||
#define CLKID_SD_EMMC_C_CLK_SEL (PERI_BASE + 0)
|
||||
#define CLKID_SD_EMMC_C_CLK_DIV (PERI_BASE + 1)
|
||||
#define CLKID_SD_EMMC_C_CLK (PERI_BASE + 2)
|
||||
#define CLKID_SD_EMMC_A_CLK_SEL (PERI_BASE + 3)
|
||||
#define CLKID_SD_EMMC_A_CLK_DIV (PERI_BASE + 4)
|
||||
#define CLKID_SD_EMMC_A_CLK (PERI_BASE + 5)
|
||||
#define CLKID_SD_EMMC_B_CLK_SEL (PERI_BASE + 6)
|
||||
#define CLKID_SD_EMMC_B_CLK_DIV (PERI_BASE + 7)
|
||||
#define CLKID_SD_EMMC_B_CLK (PERI_BASE + 8)
|
||||
#define CLKID_SPICC0_SEL (PERI_BASE + 9)
|
||||
#define CLKID_SPICC0_DIV (PERI_BASE + 10)
|
||||
#define CLKID_SPICC0 (PERI_BASE + 11)
|
||||
#define CLKID_SPICC1_SEL (PERI_BASE + 12)
|
||||
#define CLKID_SPICC1_DIV (PERI_BASE + 13)
|
||||
#define CLKID_SPICC1 (PERI_BASE + 14)
|
||||
#define CLKID_SPICC2_SEL (PERI_BASE + 15)
|
||||
#define CLKID_SPICC2_DIV (PERI_BASE + 16)
|
||||
#define CLKID_SPICC2 (PERI_BASE + 17)
|
||||
#define CLKID_PWM_A_SEL (PERI_BASE + 27)
|
||||
#define CLKID_PWM_A_DIV (PERI_BASE + 28)
|
||||
#define CLKID_PWM_A (PERI_BASE + 29)
|
||||
#define CLKID_PWM_B_SEL (PERI_BASE + 30)
|
||||
#define CLKID_PWM_B_DIV (PERI_BASE + 31)
|
||||
#define CLKID_PWM_B (PERI_BASE + 32)
|
||||
#define CLKID_PWM_C_SEL (PERI_BASE + 33)
|
||||
#define CLKID_PWM_C_DIV (PERI_BASE + 34)
|
||||
#define CLKID_PWM_C (PERI_BASE + 35)
|
||||
#define CLKID_PWM_D_SEL (PERI_BASE + 36)
|
||||
#define CLKID_PWM_D_DIV (PERI_BASE + 37)
|
||||
#define CLKID_PWM_D (PERI_BASE + 38)
|
||||
#define CLKID_PWM_E_SEL (PERI_BASE + 39)
|
||||
#define CLKID_PWM_E_DIV (PERI_BASE + 40)
|
||||
#define CLKID_PWM_E (PERI_BASE + 41)
|
||||
#define CLKID_PWM_F_SEL (PERI_BASE + 42)
|
||||
#define CLKID_PWM_F_DIV (PERI_BASE + 43)
|
||||
#define CLKID_PWM_F (PERI_BASE + 44)
|
||||
#define CLKID_PWM_G_SEL (PERI_BASE + 45)
|
||||
#define CLKID_PWM_G_DIV (PERI_BASE + 46)
|
||||
#define CLKID_PWM_G (PERI_BASE + 47)
|
||||
#define CLKID_PWM_H_SEL (PERI_BASE + 48)
|
||||
#define CLKID_PWM_H_DIV (PERI_BASE + 49)
|
||||
#define CLKID_PWM_H (PERI_BASE + 50)
|
||||
#define CLKID_PWM_I_SEL (PERI_BASE + 51)
|
||||
#define CLKID_PWM_I_DIV (PERI_BASE + 52)
|
||||
#define CLKID_PWM_I (PERI_BASE + 53)
|
||||
#define CLKID_PWM_J_SEL (PERI_BASE + 54)
|
||||
#define CLKID_PWM_J_DIV (PERI_BASE + 55)
|
||||
#define CLKID_PWM_J (PERI_BASE + 56)
|
||||
#define CLKID_SARADC_SEL (PERI_BASE + 57)
|
||||
#define CLKID_SARADC_DIV (PERI_BASE + 58)
|
||||
#define CLKID_SARADC (PERI_BASE + 59)
|
||||
#define CLKID_GEN_SEL (PERI_BASE + 60)
|
||||
#define CLKID_GEN_DIV (PERI_BASE + 61)
|
||||
#define CLKID_GEN (PERI_BASE + 62)
|
||||
#define CLKID_ETH_RMII_SEL (PERI_BASE + 63)
|
||||
#define CLKID_ETH_RMII_DIV (PERI_BASE + 64)
|
||||
#define CLKID_ETH_RMII (PERI_BASE + 65)
|
||||
#define CLKID_ETH_DIV8 (PERI_BASE + 66)
|
||||
#define CLKID_ETH_125M (PERI_BASE + 67)
|
||||
#define CLKID_TS_CLK_DIV (PERI_BASE + 68)
|
||||
#define CLKID_TS_CLK (PERI_BASE + 69)
|
||||
#define CLKID_USB_250M_SEL (PERI_BASE + 70)
|
||||
#define CLKID_USB_250M_DIV (PERI_BASE + 71)
|
||||
#define CLKID_USB_250M (PERI_BASE + 72)
|
||||
#define CLKID_PCIE_400M_SEL (PERI_BASE + 73)
|
||||
#define CLKID_PCIE_400M_DIV (PERI_BASE + 74)
|
||||
#define CLKID_PCIE_400M (PERI_BASE + 75)
|
||||
#define CLKID_PCIE_CLK_SEL (PERI_BASE + 76)
|
||||
#define CLKID_PCIE_CLK_DIV (PERI_BASE + 77)
|
||||
#define CLKID_PCIE_CLK (PERI_BASE + 78)
|
||||
#define CLKID_PCIE_TL_CLK_SEL (PERI_BASE + 79)
|
||||
#define CLKID_PCIE_TL_CLK_DIV (PERI_BASE + 80)
|
||||
#define CLKID_PCIE_TL_CLK (PERI_BASE + 81)
|
||||
#define CLKID_CDAC_SEL (PERI_BASE + 82)
|
||||
#define CLKID_CDAC_DIV (PERI_BASE + 83)
|
||||
#define CLKID_CDAC (PERI_BASE + 84)
|
||||
#define CLKID_SC_SEL (PERI_BASE + 85)
|
||||
#define CLKID_SC_DIV (PERI_BASE + 86)
|
||||
#define CLKID_SC (PERI_BASE + 87)
|
||||
|
||||
#define MEDIA_BASE (PERI_BASE + 88)
|
||||
#define CLKID_VAPB_0_SEL (MEDIA_BASE + 1)
|
||||
#define CLKID_VAPB_0_DIV (MEDIA_BASE + 2)
|
||||
#define CLKID_VAPB_0 (MEDIA_BASE + 3)
|
||||
#define CLKID_GE2D_SEL (MEDIA_BASE + 4)
|
||||
#define CLKID_GE2D_DIV (MEDIA_BASE + 5)
|
||||
#define CLKID_GE2D (MEDIA_BASE + 6)
|
||||
#define CLKID_NNA_0_SEL (MEDIA_BASE + 7)
|
||||
#define CLKID_NNA_0_DIV (MEDIA_BASE + 8)
|
||||
#define CLKID_NNA_0 (MEDIA_BASE + 9)
|
||||
#define CLKID_NNA_1_SEL (MEDIA_BASE + 10)
|
||||
#define CLKID_NNA_1_DIV (MEDIA_BASE + 11)
|
||||
#define CLKID_NNA_1 (MEDIA_BASE + 12)
|
||||
#define CLKID_NNA_SEL (MEDIA_BASE + 13)
|
||||
#define CLKID_NNA (MEDIA_BASE + 14)
|
||||
#define CLKID_VPU0_SEL (MEDIA_BASE + 15)
|
||||
#define CLKID_VPU0_DIV (MEDIA_BASE + 16)
|
||||
#define CLKID_VPU0 (MEDIA_BASE + 17)
|
||||
#define CLKID_VPU1_SEL (MEDIA_BASE + 18)
|
||||
#define CLKID_VPU1_DIV (MEDIA_BASE + 19)
|
||||
#define CLKID_VPU1 (MEDIA_BASE + 20)
|
||||
#define CLKID_VPU_SEL (MEDIA_BASE + 21)
|
||||
#define CLKID_VPU (MEDIA_BASE + 22)
|
||||
#define CLKID_VPU_CLKB_TMP_SEL (MEDIA_BASE + 23)
|
||||
#define CLKID_VPU_CLKB_TMP_DIV (MEDIA_BASE + 24)
|
||||
#define CLKID_VPU_CLKB_TMP (MEDIA_BASE + 25)
|
||||
#define CLKID_VPU_CLKB_DIV (MEDIA_BASE + 26)
|
||||
#define CLKID_VPU_CLKB (MEDIA_BASE + 27)
|
||||
#define CLKID_VIN_MEAS_SEL (MEDIA_BASE + 28)
|
||||
#define CLKID_VIN_MEAS_DIV (MEDIA_BASE + 29)
|
||||
#define CLKID_VIN_MEAS (MEDIA_BASE + 30)
|
||||
#define CLKID_VID_LOCK_SEL (MEDIA_BASE + 31)
|
||||
#define CLKID_VID_LOCK_DIV (MEDIA_BASE + 32)
|
||||
#define CLKID_VID_LOCK (MEDIA_BASE + 33)
|
||||
#define CLKID_CMPR_SEL (MEDIA_BASE + 34)
|
||||
#define CLKID_CMPR_DIV (MEDIA_BASE + 35)
|
||||
#define CLKID_CMPR (MEDIA_BASE + 36)
|
||||
#define CLKID_MALI0_SEL (MEDIA_BASE + 37)
|
||||
#define CLKID_MALI0_DIV (MEDIA_BASE + 38)
|
||||
#define CLKID_MALI0 (MEDIA_BASE + 39)
|
||||
#define CLKID_MALI1_SEL (MEDIA_BASE + 40)
|
||||
#define CLKID_MALI1_DIV (MEDIA_BASE + 41)
|
||||
#define CLKID_MALI1 (MEDIA_BASE + 42)
|
||||
#define CLKID_MALI_SEL (MEDIA_BASE + 43)
|
||||
#define CLKID_MALI (MEDIA_BASE + 44)
|
||||
#define CLKID_VDEC0_SEL (MEDIA_BASE + 45)
|
||||
#define CLKID_VDEC0_DIV (MEDIA_BASE + 46)
|
||||
#define CLKID_VDEC0 (MEDIA_BASE + 47)
|
||||
#define CLKID_VDEC1_SEL (MEDIA_BASE + 48)
|
||||
#define CLKID_VDEC1_DIV (MEDIA_BASE + 49)
|
||||
#define CLKID_VDEC1 (MEDIA_BASE + 50)
|
||||
#define CLKID_VDEC_SEL (MEDIA_BASE + 51)
|
||||
#define CLKID_VDEC (MEDIA_BASE + 52)
|
||||
#define CLKID_HCODEC0_SEL (MEDIA_BASE + 53)
|
||||
#define CLKID_HCODEC0_DIV (MEDIA_BASE + 54)
|
||||
#define CLKID_HCODEC0 (MEDIA_BASE + 55)
|
||||
#define CLKID_HCODEC1_SEL (MEDIA_BASE + 56)
|
||||
#define CLKID_HCODEC1_DIV (MEDIA_BASE + 57)
|
||||
#define CLKID_HCODEC1 (MEDIA_BASE + 58)
|
||||
#define CLKID_HCODEC_SEL (MEDIA_BASE + 59)
|
||||
#define CLKID_HCODEC (MEDIA_BASE + 60)
|
||||
#define CLKID_HEVC0_SEL (MEDIA_BASE + 61)
|
||||
#define CLKID_HEVC0_DIV (MEDIA_BASE + 62)
|
||||
#define CLKID_HEVC0 (MEDIA_BASE + 63)
|
||||
#define CLKID_HEVC1_SEL (MEDIA_BASE + 64)
|
||||
#define CLKID_HEVC1_DIV (MEDIA_BASE + 65)
|
||||
#define CLKID_HEVC1 (MEDIA_BASE + 66)
|
||||
#define CLKID_HEVC_SEL (MEDIA_BASE + 67)
|
||||
#define CLKID_HEVC (MEDIA_BASE + 68)
|
||||
#define CLKID_VC9000E_AXI_SEL (MEDIA_BASE + 69)
|
||||
#define CLKID_VC9000E_AXI_DIV (MEDIA_BASE + 70)
|
||||
#define CLKID_VC9000E_AXI (MEDIA_BASE + 71)
|
||||
#define CLKID_VC9000E_CORE_SEL (MEDIA_BASE + 72)
|
||||
#define CLKID_VC9000E_CORE_DIV (MEDIA_BASE + 73)
|
||||
#define CLKID_VC9000E_CORE (MEDIA_BASE + 74)
|
||||
#define CLKID_HDMITX_SYS_SEL (MEDIA_BASE + 75)
|
||||
#define CLKID_HDMITX_SYS_DIV (MEDIA_BASE + 76)
|
||||
#define CLKID_HDMITX_SYS (MEDIA_BASE + 77)
|
||||
#define CLKID_HDMITX_PRIF_SEL (MEDIA_BASE + 78)
|
||||
#define CLKID_HDMITX_PRIF_DIV (MEDIA_BASE + 79)
|
||||
#define CLKID_HDMITX_PRIF (MEDIA_BASE + 80)
|
||||
#define CLKID_HDMITX_200M_SEL (MEDIA_BASE + 81)
|
||||
#define CLKID_HDMITX_200M_DIV (MEDIA_BASE + 82)
|
||||
#define CLKID_HDMITX_200M (MEDIA_BASE + 83)
|
||||
#define CLKID_HDMITX_AUD_SEL (MEDIA_BASE + 84)
|
||||
#define CLKID_HDMITX_AUD_DIV (MEDIA_BASE + 85)
|
||||
#define CLKID_HDMITX_AUD (MEDIA_BASE + 86)
|
||||
#define CLKID_ENC_HDMI_TX_PNX_SEL (MEDIA_BASE + 87)
|
||||
#define CLKID_ENC_HDMI_TX_PNX (MEDIA_BASE + 88)
|
||||
#define CLKID_ENC_HDMI_TX_FE_SEL (MEDIA_BASE + 89)
|
||||
#define CLKID_ENC_HDMI_TX_FE (MEDIA_BASE + 90)
|
||||
#define CLKID_ENC_HDMI_TX_PIXEL_SEL (MEDIA_BASE + 91)
|
||||
#define CLKID_ENC_HDMI_TX_PIXEL (MEDIA_BASE + 92)
|
||||
#define CLKID_HDMI_TX_PNX_SEL (MEDIA_BASE + 93)
|
||||
#define CLKID_HDMI_TX_FE_SEL (MEDIA_BASE + 94)
|
||||
#define CLKID_HDMI_TX_PIXEL_SEL (MEDIA_BASE + 95)
|
||||
#define CLKID_HDMI_TX_PNX_DIV (MEDIA_BASE + 96)
|
||||
#define CLKID_HDMI_TX_FE_DIV (MEDIA_BASE + 97)
|
||||
#define CLKID_HDMI_TX_PIXEL_DIV (MEDIA_BASE + 98)
|
||||
#define CLKID_HDMI_TX_PNX (MEDIA_BASE + 99)
|
||||
#define CLKID_HDMI_TX_FE (MEDIA_BASE + 100)
|
||||
#define CLKID_HDMI_TX_PIXEL (MEDIA_BASE + 101)
|
||||
#define CLKID_HTX_TMDS_SEL (MEDIA_BASE + 102)
|
||||
#define CLKID_HTX_TMDS_DIV (MEDIA_BASE + 103)
|
||||
#define CLKID_HTX_TMDS (MEDIA_BASE + 104)
|
||||
|
||||
#define SYS_BASE (MEDIA_BASE + 105)
|
||||
#define CLKID_SYS_CLK_DDR (SYS_BASE + 0)
|
||||
#define CLKID_SYS_CLK_ETHPHY (SYS_BASE + 1)
|
||||
#define CLKID_SYS_CLK_GPU (SYS_BASE + 2)
|
||||
#define CLKID_SYS_CLK_VC9000E (SYS_BASE + 3)
|
||||
#define CLKID_SYS_CLK_AOCPU (SYS_BASE + 4)
|
||||
#define CLKID_SYS_CLK_AUCPU (SYS_BASE + 5)
|
||||
#define CLKID_SYS_CLK_DEWARPC (SYS_BASE + 6)
|
||||
#define CLKID_SYS_CLK_DEWARPB (SYS_BASE + 7)
|
||||
#define CLKID_SYS_CLK_DEWARPA (SYS_BASE + 8)
|
||||
#define CLKID_SYS_CLK_AMPIPE_NAND (SYS_BASE + 9)
|
||||
#define CLKID_SYS_CLK_AMPIPE_ETH (SYS_BASE + 10)
|
||||
#define CLKID_SYS_CLK_AM2AXI0 (SYS_BASE + 11)
|
||||
#define CLKID_SYS_CLK_IR_CTRL (SYS_BASE + 12)
|
||||
#define CLKID_SYS_CLK_SD_EMMC_B (SYS_BASE + 13)
|
||||
#define CLKID_SYS_CLK_SD_EMMC_A (SYS_BASE + 14)
|
||||
#define CLKID_SYS_CLK_SD_EMMC_C (SYS_BASE + 15)
|
||||
#define CLKID_SYS_CLK_SPIFC (SYS_BASE + 16)
|
||||
#define CLKID_SYS_CLK_MSR_CLK (SYS_BASE + 17)
|
||||
#define CLKID_SYS_CLK_AUDIO (SYS_BASE + 18)
|
||||
#define CLKID_SYS_CLK_ETH (SYS_BASE + 19)
|
||||
#define CLKID_SYS_CLK_UART_A (SYS_BASE + 20)
|
||||
#define CLKID_SYS_CLK_UART_B (SYS_BASE + 21)
|
||||
#define CLKID_SYS_CLK_UART_C (SYS_BASE + 22)
|
||||
#define CLKID_SYS_CLK_UART_D (SYS_BASE + 23)
|
||||
#define CLKID_SYS_CLK_UART_E (SYS_BASE + 24)
|
||||
#define CLKID_SYS_CLK_UART_F (SYS_BASE + 25)
|
||||
#define CLKID_SYS_CLK_DOS (SYS_BASE + 26)
|
||||
#define CLKID_SYS_CLK_SPICC2 (SYS_BASE + 27)
|
||||
#define CLKID_SYS_CLK_ACODEC (SYS_BASE + 28)
|
||||
#define CLKID_SYS_CLK_TS_A55 (SYS_BASE + 29)
|
||||
#define CLKID_SYS_CLK_SMART_CARD (SYS_BASE + 30)
|
||||
#define CLKID_SYS_CLK_G2D (SYS_BASE + 31)
|
||||
#define CLKID_SYS_CLK_SPICC0 (SYS_BASE + 32)
|
||||
#define CLKID_SYS_CLK_SPICC1 (SYS_BASE + 33)
|
||||
#define CLKID_SYS_CLK_PCIE (SYS_BASE + 34)
|
||||
#define CLKID_SYS_CLK_PCIEPHY (SYS_BASE + 35)
|
||||
#define CLKID_SYS_CLK_USB (SYS_BASE + 36)
|
||||
#define CLKID_SYS_CLK_PCIE_PHY0 (SYS_BASE + 37)
|
||||
#define CLKID_SYS_CLK_PCIE_PHY1 (SYS_BASE + 38)
|
||||
#define CLKID_SYS_CLK_PCIE_PHY2 (SYS_BASE + 39)
|
||||
#define CLKID_SYS_CLK_I2C_M_A (SYS_BASE + 40)
|
||||
#define CLKID_SYS_CLK_I2C_M_B (SYS_BASE + 41)
|
||||
#define CLKID_SYS_CLK_I2C_M_C (SYS_BASE + 42)
|
||||
#define CLKID_SYS_CLK_I2C_M_D (SYS_BASE + 43)
|
||||
#define CLKID_SYS_CLK_I2C_M_E (SYS_BASE + 44)
|
||||
#define CLKID_SYS_CLK_I2C_M_F (SYS_BASE + 45)
|
||||
#define CLKID_SYS_CLK_TS_GPU (SYS_BASE + 46)
|
||||
#define CLKID_SYS_CLK_I2C_S_A (SYS_BASE + 47)
|
||||
#define CLKID_SYS_CLK_CMPR (SYS_BASE + 48)
|
||||
#define CLKID_SYS_CLK_MMC_PCLK (SYS_BASE + 49)
|
||||
#define CLKID_SYS_CLK_HDMITX_PCLK (SYS_BASE + 50)
|
||||
#define CLKID_SYS_CLK_HDMI20_AES_CLK (SYS_BASE + 51)
|
||||
#define CLKID_SYS_CLK_PCLK_SYS_CPU_APB (SYS_BASE + 52)
|
||||
#define CLKID_SYS_CLK_CEC (SYS_BASE + 53)
|
||||
#define CLKID_SYS_CLK_VPU_INTR (SYS_BASE + 54)
|
||||
#define CLKID_SYS_CLK_SAR_ADC (SYS_BASE + 55)
|
||||
#define CLKID_SYS_CLK_GIC (SYS_BASE + 56)
|
||||
#define CLKID_SYS_CLK_TS_NNA (SYS_BASE + 57)
|
||||
#define CLKID_SYS_CLK_PWM_AB (SYS_BASE + 58)
|
||||
#define CLKID_SYS_CLK_PWM_CD (SYS_BASE + 59)
|
||||
#define CLKID_SYS_CLK_PWM_EF (SYS_BASE + 60)
|
||||
#define CLKID_SYS_CLK_PWM_GH (SYS_BASE + 61)
|
||||
#define CLKID_SYS_CLK_PWM_IJ (SYS_BASE + 62)
|
||||
#define CLKID_SYS_CLK_TS_VPU (SYS_BASE + 63)
|
||||
#define CLKID_SYS_CLK_TS_DOS (SYS_BASE + 64)
|
||||
#define NR_CLKS (SYS_BASE + 65)
|
||||
|
||||
#endif /* __S5_CLKC_H */
|
||||
@@ -62,6 +62,9 @@
|
||||
#define VPP_POSTBLEND_OUT_PORT 18
|
||||
#define VIDEO1_PORT 19
|
||||
#define VIDEO2_PORT 20
|
||||
#define VPP2_BLOCK 21
|
||||
#define HDR3_BLOCK 22
|
||||
#define SLICE2PPC_BLOCK 23
|
||||
|
||||
/*
|
||||
* vpu block type
|
||||
|
||||
@@ -0,0 +1,138 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON_S5_GPIO_H
|
||||
#define _DT_BINDINGS_MESON_S5_GPIO_H
|
||||
|
||||
#define GPIOD_0 0
|
||||
#define GPIOD_1 1
|
||||
#define GPIOD_2 2
|
||||
#define GPIOD_3 3
|
||||
#define GPIOD_4 4
|
||||
#define GPIOD_5 5
|
||||
#define GPIOD_6 6
|
||||
#define GPIOD_7 7
|
||||
#define GPIOD_8 8
|
||||
#define GPIOD_9 9
|
||||
#define GPIOD_10 10
|
||||
#define GPIOD_11 11
|
||||
|
||||
#define GPIOE_0 12
|
||||
#define GPIOE_1 13
|
||||
#define GPIOE_2 14
|
||||
#define GPIOE_3 15
|
||||
#define GPIOE_4 16
|
||||
|
||||
#define GPIOC_0 17
|
||||
#define GPIOC_1 18
|
||||
#define GPIOC_2 19
|
||||
#define GPIOC_3 20
|
||||
#define GPIOC_4 21
|
||||
#define GPIOC_5 22
|
||||
#define GPIOC_6 23
|
||||
#define GPIOC_7 24
|
||||
|
||||
#define GPIOX_0 25
|
||||
#define GPIOX_1 26
|
||||
#define GPIOX_2 27
|
||||
#define GPIOX_3 28
|
||||
#define GPIOX_4 29
|
||||
#define GPIOX_5 30
|
||||
#define GPIOX_6 31
|
||||
#define GPIOX_7 32
|
||||
#define GPIOX_8 33
|
||||
#define GPIOX_9 34
|
||||
#define GPIOX_10 35
|
||||
#define GPIOX_11 36
|
||||
#define GPIOX_12 37
|
||||
#define GPIOX_13 38
|
||||
#define GPIOX_14 39
|
||||
#define GPIOX_15 40
|
||||
#define GPIOX_16 41
|
||||
#define GPIOX_17 42
|
||||
#define GPIOX_18 43
|
||||
#define GPIOX_19 44
|
||||
|
||||
#define GPIOH_0 45
|
||||
#define GPIOH_1 46
|
||||
#define GPIOH_2 47
|
||||
#define GPIOH_3 48
|
||||
#define GPIOH_4 49
|
||||
#define GPIOH_5 50
|
||||
#define GPIOH_6 51
|
||||
#define GPIOH_7 52
|
||||
#define GPIOH_8 53
|
||||
|
||||
#define GPIOZ_0 54
|
||||
#define GPIOZ_1 55
|
||||
#define GPIOZ_2 56
|
||||
#define GPIOZ_3 57
|
||||
#define GPIOZ_4 58
|
||||
#define GPIOZ_5 59
|
||||
#define GPIOZ_6 60
|
||||
#define GPIOZ_7 61
|
||||
#define GPIOZ_8 62
|
||||
#define GPIOZ_9 63
|
||||
#define GPIOZ_10 64
|
||||
#define GPIOZ_11 65
|
||||
#define GPIOZ_12 66
|
||||
#define GPIOZ_13 67
|
||||
#define GPIOZ_14 68
|
||||
#define GPIOZ_15 69
|
||||
|
||||
#define GPIOT_0 70
|
||||
#define GPIOT_1 71
|
||||
#define GPIOT_2 72
|
||||
#define GPIOT_3 73
|
||||
#define GPIOT_4 74
|
||||
#define GPIOT_5 75
|
||||
#define GPIOT_6 76
|
||||
#define GPIOT_7 77
|
||||
#define GPIOT_8 78
|
||||
#define GPIOT_9 79
|
||||
#define GPIOT_10 80
|
||||
#define GPIOT_11 81
|
||||
#define GPIOT_12 82
|
||||
#define GPIOT_13 83
|
||||
#define GPIOT_14 84
|
||||
#define GPIOT_15 85
|
||||
#define GPIOT_16 86
|
||||
#define GPIOT_17 87
|
||||
#define GPIOT_18 88
|
||||
#define GPIOT_19 89
|
||||
#define GPIOT_20 90
|
||||
#define GPIOT_21 91
|
||||
#define GPIOT_22 92
|
||||
#define GPIOT_23 93
|
||||
#define GPIOT_24 94
|
||||
|
||||
#define GPIOA_0 95
|
||||
#define GPIOA_1 96
|
||||
#define GPIOA_2 97
|
||||
#define GPIOA_3 98
|
||||
#define GPIOA_4 99
|
||||
#define GPIOA_5 100
|
||||
#define GPIOA_6 101
|
||||
#define GPIOA_7 102
|
||||
#define GPIOA_8 103
|
||||
#define GPIOA_9 104
|
||||
#define GPIOA_10 105
|
||||
#define GPIO_TEST_N 106
|
||||
|
||||
#define GPIOB_0 0
|
||||
#define GPIOB_1 1
|
||||
#define GPIOB_2 2
|
||||
#define GPIOB_3 3
|
||||
#define GPIOB_4 4
|
||||
#define GPIOB_5 5
|
||||
#define GPIOB_6 6
|
||||
#define GPIOB_7 7
|
||||
#define GPIOB_8 8
|
||||
#define GPIOB_9 9
|
||||
#define GPIOB_10 10
|
||||
#define GPIOB_11 11
|
||||
#define GPIOB_12 12
|
||||
|
||||
#endif /* _DT_BINDINGS_MESON_S5_GPIO_H */
|
||||
@@ -0,0 +1,39 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#define PDID_S5_MALI_0 0
|
||||
#define PDID_S5_MALI_1 1
|
||||
#define PDID_S5_MALI_2 2
|
||||
#define PDID_S5_MALI_TOP 3
|
||||
#define PDID_S5_DOS_TOP_WRAP 4
|
||||
#define PDID_S5_DOS_VDEC 5
|
||||
#define PDID_S5_DOS_HCODEC 6
|
||||
#define PDID_S5_DOS_HEVC_TOP 7
|
||||
#define PDID_S5_DOS_HEVC_CORE1 8
|
||||
#define PDID_S5_USB2 9
|
||||
#define PDID_S5_PCIE0 10
|
||||
#define PDID_S5_GE2D 11
|
||||
#define PDID_S5_VC9000E 12
|
||||
#define PDID_S5_VICP 13
|
||||
#define PDID_S5_VGE_TOP 14
|
||||
#define PDID_S5_VI_CLK1 15
|
||||
#define PDID_S5_VI_CLK2 16
|
||||
#define PDID_S5_VPU_HDMI 17
|
||||
#define PDID_S5_ETH 18
|
||||
#define PDID_S5_PCIE1 19
|
||||
#define PDID_S5_VPU_DOLBY 20
|
||||
#define PDID_S5_USB30 21
|
||||
#define PDID_S5_USB31 22
|
||||
#define PDID_S5_SDCARD 23
|
||||
#define PDID_S5_SDIO 24
|
||||
#define PDID_S5_NAND_EMMC 25
|
||||
#define PDID_S5_NNA_4T 26
|
||||
#define PDID_S5_DMC00 27
|
||||
#define PDID_S5_DMC01 28
|
||||
#define PDID_S5_NOC_DMC_TOP 29
|
||||
#define PDID_S5_DMC10 30
|
||||
#define PDID_S5_DMC11 31
|
||||
#define PDID_S5_DDRPHY0 32
|
||||
#define PDID_S5_DDRPHY1 33
|
||||
@@ -0,0 +1,221 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_S5_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON_S5_RESET_H
|
||||
|
||||
/* RESET0 */
|
||||
/* 0 */
|
||||
#define RESET_U3X1_M31_UTMI 1
|
||||
#define RESET_U3X0_M31_UTMI 2
|
||||
#define RESET_U2DRDX0 3
|
||||
/* 4 */
|
||||
#define RESET_U3DRDX1 5
|
||||
#define RESET_U3DRDX0 6
|
||||
/* 7 */
|
||||
#define RESET_U2PHY20 8
|
||||
#define RESET_U3X1_PCIE_PHY 9
|
||||
#define RESET_U3X0_PCIE_PHY 10
|
||||
#define RESET_APB_DECODE_DMC 11
|
||||
/* 12-15 */
|
||||
#define RESET_BRG_SYS_APB_DEC 16
|
||||
#define RESET_BRG_VCBUS_DEC 17
|
||||
#define RESET_HDMITX_CAPB3 18
|
||||
#define RESET_HDMITX 19
|
||||
/* 20 */
|
||||
#define RESET_GE2D 21
|
||||
/* 22 */
|
||||
#define RESET_HTXDPHY 23
|
||||
#define RESET_HDMI20_AES 24
|
||||
/* 25-28 */
|
||||
#define RESET_DSC_ENC_CAPB3 29
|
||||
#define RESET_DSC_ENC 30
|
||||
/* 31 */
|
||||
|
||||
/* RESET1 */
|
||||
#define RESET_AUDIO 32
|
||||
#define RESET_DOS 33
|
||||
#define RESET_DOS_CAPB3 34
|
||||
#define RESET_DDR_APB 35
|
||||
#define RESET_DDR 36
|
||||
/* 37 */
|
||||
#define RESET_U3X1_PCIE_APB 38
|
||||
#define RESET_U3X0_PCIE_APB 39
|
||||
#define RESET_I_DEBUGB 40
|
||||
#define RESET_I_DEBUGA 41
|
||||
/* 42-43 */
|
||||
#define RESET_PCIE_GEN2_L1 44
|
||||
#define RESET_PCIE_B_APB 45
|
||||
#define RESET_PCIE_A_APB 46
|
||||
#define RESET_ADLA 47
|
||||
#define RESET_ETH 48
|
||||
/* 49 */
|
||||
#define RESET_PCIE_GEN2_L0 50
|
||||
/* 51 */
|
||||
#define RESET_U3COMBX1 52
|
||||
#define RESET_U3COMBX0 53
|
||||
#define RESET_U2COMBX0 54
|
||||
#define RESET_NNA_NIC_4T 55
|
||||
/* 56-58 */
|
||||
#define RESET_NNA_NIC_1T 59
|
||||
#define RESET_NNA_NIC_MAIN 60
|
||||
#define RESET_NNA_NIC_GPV 61
|
||||
#define RESET_NNA_NIC_ALL 62
|
||||
#define RESET_ACODEC 63
|
||||
|
||||
/* RESET2 */
|
||||
#define RESET_IR_CTRL 64
|
||||
#define RESET_TS_A55 65
|
||||
/* 66-67 */
|
||||
#define RESET_SPICC_2 68
|
||||
/* 69-71 */
|
||||
#define RESET_SMART_CARD 72
|
||||
#define RESET_SPICC_0 73
|
||||
#define RESET_SPICC_1 74
|
||||
/* 75-79 */
|
||||
#define RESET_MSR_CLK 80
|
||||
#define RESET_SPIFC 81
|
||||
#define RESET_SAR_ADC 82
|
||||
/* 83-88 */
|
||||
#define RESET_CEC 89
|
||||
#define RESET_AFIFO 90
|
||||
#define RESET_WATCHDOG 91
|
||||
#define RESET_VID_PLL0_DIV 92
|
||||
/* 93 */
|
||||
#define RESET_TMDS20_DIV 94
|
||||
/* 95 */
|
||||
|
||||
/* RESET3 */
|
||||
/* 96-99 */
|
||||
#define RESET_PCIE_B_7 100
|
||||
#define RESET_PCIE_B_6 101
|
||||
#define RESET_PCIE_B_5 102
|
||||
#define RESET_PCIE_B_4 103
|
||||
#define RESET_PCIE_B_3 104
|
||||
#define RESET_PCIE_B_2 105
|
||||
#define RESET_PCIE_B_1 106
|
||||
#define RESET_PCIE_B_0 107
|
||||
#define RESET_PCIE_A_7 108
|
||||
#define RESET_PCIE_A_6 109
|
||||
#define RESET_PCIE_A_5 110
|
||||
#define RESET_PCIE_A_4 111
|
||||
#define RESET_PCIE_A_3 112
|
||||
#define RESET_PCIE_A_2 113
|
||||
#define RESET_PCIE_A_1 114
|
||||
#define RESET_PCIE_A_0 115
|
||||
#define RESET_VDI6 116
|
||||
#define RESET_VID_LOCK 117
|
||||
#define RESET_VENC2 118
|
||||
#define RESET_VENC1 119
|
||||
#define RESET_VENC0 120
|
||||
#define RESET_VDAC 121
|
||||
#define RESET_RDMA 122
|
||||
#define RESET_VIU 123
|
||||
#define RESET_VENC 124
|
||||
/* 125-126 */
|
||||
#define RESET_A55_ACE 127
|
||||
|
||||
/* RESET4 */
|
||||
#define RESET_PWM_AB 128
|
||||
#define RESET_PWM_CD 129
|
||||
#define RESET_PWM_EF 130
|
||||
#define RESET_PWM_GH 131
|
||||
#define RESET_PWM_IJ 132
|
||||
#define RESET_VID_CMPR 133
|
||||
#define RESET_VC9000E_ARESET 134
|
||||
#define RESET_VC9000E_CORE 135
|
||||
/* 136 */
|
||||
#define RESET_VC9000E_APB 137
|
||||
#define RESET_UART_A 138
|
||||
#define RESET_UART_B 139
|
||||
#define RESET_UART_C 140
|
||||
#define RESET_UART_D 141
|
||||
#define RESET_UART_E 142
|
||||
#define RESET_UART_F 143
|
||||
#define RESET_I2C_S_A 144
|
||||
#define RESET_I2C_M_A 145
|
||||
#define RESET_I2C_M_B 146
|
||||
#define RESET_I2C_M_C 147
|
||||
#define RESET_I2C_M_D 148
|
||||
#define RESET_I2C_M_E 149
|
||||
#define RESET_I2C_M_F 150
|
||||
/* 151 */
|
||||
#define RESET_UART_G 152
|
||||
#define RESET_SD_EMMC_A 153
|
||||
#define RESET_SD_EMMC_B 154
|
||||
#define RESET_SD_EMMC_C 155
|
||||
#define RESET_TS_GPU 156
|
||||
#define RESET_TS_NNA 157
|
||||
#define RESET_TS_VPU 158
|
||||
#define RESET_TS_DOS 159
|
||||
|
||||
/* RESET5 */
|
||||
/* 160-177 */
|
||||
#define RESET_BRG_NICSYS_NPU 178
|
||||
#define RESET_BRG_NICSYS_EMMCC 179
|
||||
#define RESET_BRG_NICSYS_EMMCB 180
|
||||
#define RESET_BRG_NICSYS_EMMCA 181
|
||||
/* 182 */
|
||||
#define RESET_BRG_NICSYS_PCIE 183
|
||||
#define RESET_BRG_NICSYS_SYSCPU 184
|
||||
#define RESET_BRG_NICSYS_SYS 185
|
||||
/* 186-188 */
|
||||
#define RESET_BRG_NICSYS_VAPB 189
|
||||
#define RESET_BRG_NICSYS_MAIN 190
|
||||
#define RESET_BRG_NICSYS_ALL 191
|
||||
|
||||
/* RESET6 */
|
||||
#define RESET_BRG_AHB_PIPE_NICDOS 192
|
||||
#define RESET_BRG_AHB_PIPE_NICNNA 193
|
||||
#define RESET_BRG_AHB_PIPE_NICVPU 194
|
||||
#define RESET_BRG_AHB_PIPE_NICVGE 195
|
||||
/* 196 */
|
||||
#define RESET_BRG_AHB_PIPE_NICSYS 197
|
||||
#define RESET_BRG_VDEC_DMC_PIPEL 198
|
||||
#define RESET_BRG_HEVCF_DMC_PIPEL 199
|
||||
/* 200 */
|
||||
#define RESET_BRG_AXI_PIPE_NNATODDR 201
|
||||
/* 202 */
|
||||
#define RESET_BRG_AXI_PIPE_NNATOSYS 203
|
||||
#define RESET_BRG_AXI_PIPE_NICVPU 204
|
||||
#define RESET_BRG_AXI_PIPE_NICDOS 205
|
||||
#define RESET_BRG_AXI_PIPE_NICVGE 206
|
||||
#define RESET_BRG_AXI_PIPE_EMMCC 207
|
||||
#define RESET_BRG_APB_PIPE_NNA 208
|
||||
#define RESET_BRG_APB_PIPE_FDLETOP 209
|
||||
#define RESET_BRG_APB_PIPE_NOCDMC 210
|
||||
#define RESET_BRG_APB_PIPE_DDR0 211
|
||||
#define RESET_BRG_APB_PIPE_DDR1 212
|
||||
#define RESET_BRG_APB_PIPE_GE2D 213
|
||||
#define RESET_BRG_APB_PIPE_VPU 214
|
||||
/* 215-217 */
|
||||
#define RESET_BRG_AMPIPE_NAND 218
|
||||
#define RESET_BRG_AMPIPE_ETH 219
|
||||
/* 220 */
|
||||
#define RESET_BRG_AM2AXI0 221
|
||||
/* 222-223 */
|
||||
|
||||
/* RESET7 */
|
||||
/* 224-234 */
|
||||
#define RESET_BRG_NICVGE_SYS 235
|
||||
#define RESET_BRG_NICVGE_VC9000E 236
|
||||
#define RESET_BRG_NICVGE_VID_CMPR 237
|
||||
#define RESET_BRG_NICVGE_GE2D 238
|
||||
/* 239-241 */
|
||||
#define RESET_BRG_NICVGE_MAIN 242
|
||||
#define RESET_BRG_NICVGE_ALL 243
|
||||
/* 244 */
|
||||
#define RESET_BRG_NICDOS_SYS 245
|
||||
#define RESET_BRG_NICDOS_VDEC 246
|
||||
#define RESET_BRG_NICDOS_HEVC 247
|
||||
#define RESET_BRG_NICDOS_HCODEC 248
|
||||
#define RESET_BRG_NICDOS_MAIN 249
|
||||
#define RESET_BRG_NICDOS_ALL 250
|
||||
/* 251-252 */
|
||||
#define RESET_BRG_NICVPU_SYS 253
|
||||
#define RESET_BRG_NICVPU_MAIN 254
|
||||
#define RESET_BRG_NICVPU_ALL 255
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user