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Merge "amvecm: porting amvecm kernel 5.15 for S4/A1 [1/1]" into amlogic-5.15-dev

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This commit is contained in:
Wanwei Jiang
2022-06-06 00:41:08 -07:00
committed by Gerrit Code Review
parent 5176ebdee7 f12ba6b47c
commit 1a930e64e0
20 changed files with 670 additions and 581 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/media/enhancement/amdolby_vision/amdolby_vision.c
+2 -2
View File
@@ -3973,7 +3973,7 @@ static void video_effect_bypass(int bypass)
bypass_all_vpp_pq || is_meson_tvmode())
dv_pq_ctl(DV_PQ_CERT);
else
dv_pq_ctl(DV_PQ_BYPASS);
dv_pq_ctl(DV_PQ_TV_BYPASS);
return;
} else if (debug_bypass_vpp_pq == 2) {
dv_pq_ctl(DV_PQ_REC);
@@ -4018,7 +4018,7 @@ static void video_effect_bypass(int bypass)
bypass_all_vpp_pq || is_meson_tvmode())
dv_pq_ctl(DV_PQ_CERT);
else
dv_pq_ctl(DV_PQ_BYPASS);
dv_pq_ctl(DV_PQ_TV_BYPASS);
}
} else if (is_video_effect_bypass) {
if (is_meson_txlx()) {
drivers/media/enhancement/amvecm/amcm.c
+104 -42
View File
@@ -66,7 +66,7 @@ static unsigned int cm_width_limit = 50;/* vlsi adjust */
module_param(cm_width_limit, uint, 0664);
MODULE_PARM_DESC(cm_width_limit, "\n cm_width_limit\n");
int pq_reg_wr_rdma = 1;/* 0:disabel;1:enable */
int pq_reg_wr_rdma;/* 0:disabel;1:enable */
module_param(pq_reg_wr_rdma, int, 0664);
MODULE_PARM_DESC(pq_reg_wr_rdma, "\n pq_reg_wr_rdma\n");
@@ -201,19 +201,33 @@ void am_set_regmap(struct am_regs_s *p)
}
}
VSYNC_WR_MPEG_REG(VPP_CHROMA_ADDR_PORT, addr);
if (mask == 0xffffffff) {
VSYNC_WR_MPEG_REG(VPP_CHROMA_DATA_PORT,
val);
if (pq_reg_wr_rdma) {
VSYNC_WR_MPEG_REG(VPP_CHROMA_ADDR_PORT, addr);
if (mask == 0xffffffff) {
VSYNC_WR_MPEG_REG(VPP_CHROMA_DATA_PORT,
val);
} else {
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
VSYNC_WR_MPEG_REG(VPP_CHROMA_ADDR_PORT,
addr);
VSYNC_WR_MPEG_REG(VPP_CHROMA_DATA_PORT,
(temp & (~mask)) |
(val & mask));
}
} else {
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
VSYNC_WR_MPEG_REG(VPP_CHROMA_ADDR_PORT,
addr);
VSYNC_WR_MPEG_REG(VPP_CHROMA_DATA_PORT,
(temp & (~mask)) |
(val & mask));
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, addr);
if (mask == 0xffffffff) {
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
val);
} else {
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
addr);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
(temp & (~mask)) |
(val & mask));
}
}
default_sat_param(addr, val);
break;
case REG_TYPE_INDEX_GAMMA:
@@ -323,7 +337,7 @@ void am_set_regmap(struct am_regs_s *p)
}
}
void amcm_disable(void)
void amcm_disable(enum wr_md_e md)
{
int temp;
@@ -335,26 +349,50 @@ void amcm_disable(void)
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (temp & 0x1) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
VSYNC_WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp & 0xfffffffe);
switch (md) {
case WR_VCB:
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (temp & 0x1) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp & 0xfffffffe);
}
} else {
if (temp & 0x2) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp & 0xfffffffd);
}
}
} else {
if (temp & 0x2) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
VSYNC_WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp & 0xfffffffd);
break;
case WR_DMA:
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (temp & 0x1) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
VSYNC_WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp & 0xfffffffe);
}
} else {
if (temp & 0x2) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
VSYNC_WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp & 0xfffffffd);
}
}
break;
default:
break;
}
cm_en_flag = false;
}
void amcm_enable(void)
void amcm_enable(enum wr_md_e md)
{
int temp;
@@ -362,20 +400,44 @@ void amcm_enable(void)
WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1);
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (!(temp & 0x1)) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
VSYNC_WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp | 0x1);
switch (md) {
case WR_VCB:
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (!(temp & 0x1)) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp | 0x1);
}
} else {
if (!(temp & 0x2)) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp | 0x2);
}
}
} else {
if (!(temp & 0x2)) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
VSYNC_WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp | 0x2);
break;
case WR_DMA:
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (!(temp & 0x1)) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
VSYNC_WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp | 0x1);
}
} else {
if (!(temp & 0x2)) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
0x208);
VSYNC_WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
temp | 0x2);
}
}
break;
default:
break;
}
/* enable CM histogram by default, mode 0 */
@@ -473,9 +535,9 @@ void cm2_frame_size_patch(unsigned int width, unsigned int height)
if (!cm_en)
return;
else if (width < cm_width_limit)
amcm_disable();
amcm_disable(WR_DMA);
else if ((!cm_en_flag) && (!cm_dis_flag))
amcm_enable();
amcm_enable(WR_DMA);
vpp_size = width | (height << 16);
if (cm_size != vpp_size) {
VSYNC_WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x205);
@@ -540,11 +602,11 @@ void cm_latch_process(void)
(get_cpu_type() != MESON_CPU_MAJOR_ID_T7) &&
(get_cpu_type() != MESON_CPU_MAJOR_ID_T3))
amcm_level_sel(cm_level);
amcm_enable();
amcm_enable(WR_DMA);
pr_amcm_dbg("\n[amcm..] set cm2 load OK!!!\n");
} else if ((cm_en == 0) && (cm_level_last != 0xff)) {
cm_level_last = 0xff;
amcm_disable();/* CM manage disable */
amcm_disable(WR_DMA);/* CM manage disable */
pr_amcm_dbg("\n[amcm..] set cm disable!!!\n");
}
}
drivers/media/enhancement/amvecm/amcm.h
+3 -2
View File
@@ -35,13 +35,14 @@ extern int cm_en; /* 0:disabel;1:enable */
extern int dnlp_en;/*0:disabel;1:enable */
extern unsigned int sr1_reg_val[101];
extern int pq_reg_wr_rdma;
/* *********************************************************************** */
/* *** IOCTL-oriented functions ****************************************** */
/* *********************************************************************** */
void am_set_regmap(struct am_regs_s *p);
void amcm_disable(void);
void amcm_enable(void);
void amcm_disable(enum wr_md_e md);
void amcm_enable(enum wr_md_e md);
void amcm_level_sel(unsigned int cm_level);
void cm2_frame_size_patch(unsigned int width, unsigned int height);
void cm2_frame_switch_patch(void);
drivers/media/enhancement/amvecm/amcsc.c
+17 -4
View File
@@ -58,6 +58,7 @@ uint debug_csc;
static int cur_mvc_type[VD_PATH_MAX];
static int cur_rgb_type[VD_PATH_MAX];
static int rgb_type_proc[VD_PATH_MAX];
static int cur_primesl_type[VD_PATH_MAX];
#define FORCE_RGB_PROCESS 1
module_param(debug_csc, uint, 0664);
@@ -6801,6 +6802,8 @@ static enum hdr_type_e get_source_type(enum vd_path_e vd_path, enum vpp_index vp
get_cur_vd_signal_type(vd_path);
if (cur_mvc_type[vd_path] == VIDTYPE_MVC)
return HDRTYPE_MVC;
if (cur_primesl_type[vd_path])
return HDRTYPE_PRIMESL;
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
if (vd_path == VD1_PATH &&
is_dolby_vision_enable() &&
@@ -7773,10 +7776,20 @@ static int vpp_matrix_update(struct vframe_s *vf,
signal_change_flag |= SIG_FORCE_CHG;
get_cur_vd_signal_type(vd_path);
if (force_csc_type != 0xff)
if (force_csc_type != 0xff) {
csc_type = force_csc_type;
else
cur_primesl_type[vd_path] = 0;
} else {
csc_type = get_csc_type();
/* force prime sl output as HDR */
/* TODO: check if need VD1_PATH */
if (get_vframe_src_fmt(vf) == VFRAME_SIGNAL_FMT_HDR10PRIME) {
csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB;
cur_primesl_type[vd_path] = 1;
} else {
cur_primesl_type[vd_path] = 0;
}
}
if (video_process_status[vd_path] == HDR_MODULE_BYPASS &&
!(video_process_flags[vd_path] & PROC_FLAG_FORCE_PROCESS)) {
@@ -8513,8 +8526,8 @@ hdr_dump:
hlg_process_mode[i]);
pr_info("sdr_mode:0x%x, sdr_process_mode:0x%x, cur_sdr_process_mode:0x%x\n",
sdr_mode, sdr_process_mode[i], cur_sdr_process_mode[i]);
pr_info("cur_signal_type:0x%x, cur_csc_mode:0x%x, cur_csc_type:0x%x\n",
cur_signal_type[i], cur_csc_mode, cur_csc_type[i]);
pr_info("cur_signal_type:0x%x, cur_csc_mode:0x%x, cur_csc_type:0x%x, cur_primesl_type:%d\n",
cur_signal_type[i], cur_csc_mode, cur_csc_type[i], cur_primesl_type[i]);
pr_info("hdr10_plus_process_mode = 0x%x\n",
hdr10_plus_process_mode[i]);
}
drivers/media/enhancement/amvecm/amcsc_pip.c
+31 -13
View File
@@ -602,15 +602,32 @@ int hdr_policy_process(struct vinfo_s *vinfo,
/* vd1 bypass hdr+ when vd2 off */
hdr10_plus_process_mode[vd_path] = PROC_BYPASS;
target_format[vd_path] = BT2020_PQ_DYNAMIC;
} else if (vd_path == VD2_PATH &&
is_dolby_vision_on() &&
is_dolby_vision_stb_mode()) {
/* vd2 *->ipt when vd1 dolby on */
hdr_process_mode[vd_path] = PROC_MATCH;
hlg_process_mode[vd_path] = PROC_MATCH;
sdr_process_mode[vd_path] = PROC_MATCH;
hdr10_plus_process_mode[vd_path] = PROC_MATCH;
target_format[vd_path] = BT2100_IPT;
} else if ((vd_path == VD2_PATH) &&
is_dolby_vision_on() &&
is_dolby_vision_stb_mode()) {
if (source_format[vd_path] == HDRTYPE_DOVI ||
(source_format[vd_path] == HDRTYPE_HDR10 &&
(dv_hdr_policy & 1)) ||
(source_format[vd_path] == HDRTYPE_HLG &&
(dv_hdr_policy & 2)) ||
(source_format[vd_path] == HDRTYPE_SDR/* &&*/
/* (dv_hdr_policy & 0x20)*/)) {
/* vd2 follow sink: dv handle sdr/hdr/hlg/dovi */
sdr_process_mode[vd_path] = PROC_BYPASS;
hdr_process_mode[vd_path] = PROC_BYPASS;
hlg_process_mode[vd_path] = PROC_BYPASS;
hdr10_plus_process_mode[vd_path] = PROC_BYPASS;
target_format[vd_path] = BT709;
set_hdr_module_status(vd_path, HDR_MODULE_OFF);
dolby_vision_set_toggle_flag(1);
} else {
/* vd2 *->ipt when vd1 dolby on */
hdr_process_mode[vd_path] = PROC_MATCH;
hlg_process_mode[vd_path] = PROC_MATCH;
sdr_process_mode[vd_path] = PROC_MATCH;
hdr10_plus_process_mode[vd_path] = PROC_MATCH;
target_format[vd_path] = BT2100_IPT;
}
} else if (vd_path == VD2_PATH &&
is_video_layer_on(VD1_PATH)) {
/* vd1 on and vd2 follow vd1 output */
@@ -793,6 +810,7 @@ int hdr_policy_process(struct vinfo_s *vinfo,
}
break;
case HDRTYPE_HDR10:
case HDRTYPE_PRIMESL:
/* source HDR10 */
if (sink_hdr_support(vinfo) & HDR_SUPPORT) {
/* hdr bypass */
@@ -896,6 +914,7 @@ int hdr_policy_process(struct vinfo_s *vinfo,
}
break;
case HDRTYPE_HDR10:
case HDRTYPE_PRIMESL:
/* VD2 source HDR10 */
if (target_format[oth_path] == BT2020_PQ ||
target_format[oth_path] == BT2020_PQ_DYNAMIC) {
@@ -1054,6 +1073,7 @@ int hdr_policy_process(struct vinfo_s *vinfo,
}
break;
case HDRTYPE_HDR10:
case HDRTYPE_PRIMESL:
/* VD2 source HDR10 */
if (target_format[oth_path] == BT2020_PQ ||
target_format[oth_path] == BT2020_PQ_DYNAMIC) {
@@ -1139,10 +1159,6 @@ out:
vd_path == VD2_PATH &&
is_video_layer_on(VD2_PATH) &&
target_format[vd_path] != BT2100_IPT) {
pr_csc(4, "am_vecm: vd%d output mode not match to dolby %s.\n",
vd_path + 1,
output_str[target_format[vd_path]]);
change_flag |= SIG_OUTPUT_MODE_CHG;
} else if (!is_dolby_vision_on() &&
is_video_layer_on(VD1_PATH) &&
(is_video_layer_on(VD2_PATH) &&
@@ -1162,6 +1178,7 @@ out:
PROC_OFF;
break;
case HDRTYPE_HDR10:
case HDRTYPE_PRIMESL:
cur_hdr_process_mode[oth_path] = PROC_OFF;
break;
case HDRTYPE_HLG:
@@ -1641,6 +1658,7 @@ void video_post_process(struct vframe_s *vf,
}
break;
case HDRTYPE_HDR10:
case HDRTYPE_PRIMESL:
if (vd_path == VD2_PATH &&
is_dolby_vision_on() &&
is_dolby_vision_stb_mode()) {
drivers/media/enhancement/amvecm/amve.c
+182 -81
View File
@@ -367,7 +367,7 @@ void vpp_enable_lcd_gamma_table(int viu_sel, int rdma_write)
return;
}
if (viu_sel == 1) /* viu1 vsync rdma */
if (rdma_write == 1) /* viu1 vsync rdma */
VSYNC_WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, 1, GAMMA_EN, 1);
else
WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, 1, GAMMA_EN, 1);
@@ -393,7 +393,7 @@ void vpp_disable_lcd_gamma_table(int viu_sel, int rdma_write)
return;
}
if (viu_sel == 1) /* viu1 vsync rdma */
if (rdma_write == 1) /* viu1 vsync rdma */
VSYNC_WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, 0, GAMMA_EN, 1);
else
WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, 0, GAMMA_EN, 1);
@@ -1905,10 +1905,11 @@ int vpp_set_lut3d(int bfromkey,
int d0, d1, d2, counter, size, index0, index1, idn;
u32 dwtemp, ctltemp, wrgb[3];
unsigned int combine3 = 0;
#ifdef CONFIG_AMLOGIC_ENABLE_MEDIA_FILE
#ifdef CONFIG_SET_FS
struct file *fp;
mm_segment_t fs;
loff_t pos;
#endif
#endif
if (!lut3d_en)
return 1;
@@ -1946,13 +1947,15 @@ int vpp_set_lut3d(int bfromkey,
}
#endif
} else if (bfromkey == 2) {
#ifdef CONFIG_AMLOGIC_ENABLE_MEDIA_FILE
#ifdef CONFIG_SET_FS
fp = filp_open(LUT3DBIN_PATH, O_RDONLY, 0);
if (IS_ERR(fp)) {
kfree(pkeylutall);
kfree(pkeylut);
return 1;
}
//fs = get_fs();
//set_fs(KERNEL_DS);
pos = 0;
key_len = vfs_read(fp, pkeylutall, key_len, &pos);
@@ -1962,7 +1965,8 @@ int vpp_set_lut3d(int bfromkey,
return 1;
}
filp_close(fp, NULL);
#endif
//set_fs(fs);
#endif
}
size = (4914 * 9) / 2;
@@ -2471,85 +2475,169 @@ void amve_fmetersize_config(u32 sr0_w, u32 sr0_h, u32 sr1_w, u32 sr1_h)
}
}
int vpp_pq_ctrl_config(struct pq_ctrl_s pq_cfg)
int vpp_pq_ctrl_config(struct pq_ctrl_s pq_cfg, enum wr_md_e md)
{
unsigned int i;
VSYNC_WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE,
pq_cfg.sharpness0_en, 1, 1);
VSYNC_WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE,
pq_cfg.sharpness1_en, 1, 1);
switch (md) {
case WR_VCB:
WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE,
pq_cfg.sharpness0_en, 1, 1);
if (pq_cfg.dnlp_en) {
ve_enable_dnlp();
dnlp_en = 1;
} else {
ve_disable_dnlp();
dnlp_en = 0;
}
WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE,
pq_cfg.sharpness1_en, 1, 1);
if (pq_cfg.cm_en) {
amcm_enable();
cm_en = 1;
} else {
amcm_disable();
cm_en = 0;
}
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ1_MISC,
pq_cfg.vadj1_en, 0, 1);
else
VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ_CTRL,
pq_cfg.vadj1_en, 0, 1);
VSYNC_WRITE_VPP_REG_BITS(VPP_VD1_RGB_CTRST,
pq_cfg.vd1_ctrst_en, 1, 1);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ2_MISC,
pq_cfg.vadj2_en, 0, 1);
else
VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ_CTRL,
pq_cfg.vadj2_en, 2, 1);
VSYNC_WRITE_VPP_REG_BITS(VPP_POST_RGB_CTRST,
pq_cfg.post_ctrst_en, 1, 1);
amvecm_wb_enable(pq_cfg.wb_en);
gamma_en = pq_cfg.gamma_en;
if (gamma_en) {
if (is_meson_t7_cpu()) {
for (i = 0; i < 3; i++)
vpp_enable_lcd_gamma_table(i, 1);
if (pq_cfg.dnlp_en) {
ve_enable_dnlp();
dnlp_en = 1;
} else {
vpp_enable_lcd_gamma_table(0, 1);
ve_disable_dnlp();
dnlp_en = 0;
}
} else {
if (is_meson_t7_cpu()) {
for (i = 0; i < 3; i++)
vpp_disable_lcd_gamma_table(i, 1);
if (pq_cfg.cm_en) {
amcm_enable(WR_VCB);
cm_en = 1;
} else {
vpp_disable_lcd_gamma_table(0, 1);
amcm_disable(WR_VCB);
cm_en = 0;
}
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
WRITE_VPP_REG_BITS(VPP_VADJ1_MISC,
pq_cfg.vadj1_en, 0, 1);
else
WRITE_VPP_REG_BITS(VPP_VADJ_CTRL,
pq_cfg.vadj1_en, 0, 1);
WRITE_VPP_REG_BITS(VPP_VD1_RGB_CTRST,
pq_cfg.vd1_ctrst_en, 1, 1);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
WRITE_VPP_REG_BITS(VPP_VADJ2_MISC,
pq_cfg.vadj2_en, 0, 1);
else
WRITE_VPP_REG_BITS(VPP_VADJ_CTRL,
pq_cfg.vadj2_en, 2, 1);
WRITE_VPP_REG_BITS(VPP_POST_RGB_CTRST,
pq_cfg.post_ctrst_en, 1, 1);
amvecm_wb_enable(pq_cfg.wb_en);
gamma_en = pq_cfg.gamma_en;
if (gamma_en) {
if (is_meson_t7_cpu()) {
for (i = 0; i < 3; i++)
vpp_enable_lcd_gamma_table(i, 0);
} else {
vpp_enable_lcd_gamma_table(0, 0);
}
} else {
if (is_meson_t7_cpu()) {
for (i = 0; i < 3; i++)
vpp_disable_lcd_gamma_table(i, 0);
} else {
vpp_disable_lcd_gamma_table(0, 0);
}
}
if (pq_cfg.lc_en) {
lc_en = 1;
} else {
lc_en = 0;
if (is_meson_tl1_cpu() ||
is_meson_tm2_cpu())
lc_disable();
}
WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL,
pq_cfg.black_ext_en, 3, 1);
WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL,
pq_cfg.chroma_cor_en, 4, 1);
break;
case WR_DMA:
VSYNC_WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE,
pq_cfg.sharpness0_en, 1, 1);
VSYNC_WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE,
pq_cfg.sharpness1_en, 1, 1);
if (pq_cfg.dnlp_en) {
ve_enable_dnlp();
dnlp_en = 1;
} else {
ve_disable_dnlp();
dnlp_en = 0;
}
if (pq_cfg.cm_en) {
amcm_enable(WR_DMA);
cm_en = 1;
} else {
amcm_disable(WR_DMA);
cm_en = 0;
}
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ1_MISC,
pq_cfg.vadj1_en, 0, 1);
else
VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ_CTRL,
pq_cfg.vadj1_en, 0, 1);
VSYNC_WRITE_VPP_REG_BITS(VPP_VD1_RGB_CTRST,
pq_cfg.vd1_ctrst_en, 1, 1);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ2_MISC,
pq_cfg.vadj2_en, 0, 1);
else
VSYNC_WRITE_VPP_REG_BITS(VPP_VADJ_CTRL,
pq_cfg.vadj2_en, 2, 1);
VSYNC_WRITE_VPP_REG_BITS(VPP_POST_RGB_CTRST,
pq_cfg.post_ctrst_en, 1, 1);
amvecm_wb_enable(pq_cfg.wb_en);
gamma_en = pq_cfg.gamma_en;
if (gamma_en) {
if (is_meson_t7_cpu()) {
for (i = 0; i < 3; i++)
vpp_enable_lcd_gamma_table(i, 1);
} else {
vpp_enable_lcd_gamma_table(0, 1);
}
} else {
if (is_meson_t7_cpu()) {
for (i = 0; i < 3; i++)
vpp_disable_lcd_gamma_table(i, 1);
} else {
vpp_disable_lcd_gamma_table(0, 1);
}
}
if (pq_cfg.lc_en) {
lc_en = 1;
} else {
lc_en = 0;
if (is_meson_tl1_cpu() ||
is_meson_tm2_cpu())
lc_disable();
}
VSYNC_WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL,
pq_cfg.black_ext_en, 3, 1);
VSYNC_WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL,
pq_cfg.chroma_cor_en, 4, 1);
break;
default:
break;
}
if (pq_cfg.lc_en) {
lc_en = 1;
} else {
lc_en = 0;
if (is_meson_tl1_cpu() ||
is_meson_tm2_cpu())
lc_disable();
}
VSYNC_WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL,
pq_cfg.black_ext_en, 3, 1);
VSYNC_WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL,
pq_cfg.chroma_cor_en, 4, 1);
return 0;
}
@@ -2558,9 +2646,13 @@ unsigned int skip_pq_ctrl_load(struct am_reg_s *p)
unsigned int ret = 0;
struct pq_ctrl_s cfg;
if (dv_pq_bypass == 2) {
if (dv_pq_bypass == 3) {
memcpy(&cfg, &dv_cfg_bypass, sizeof(struct pq_ctrl_s));
cfg.vadj1_en = pq_cfg.vadj1_en;
} else if (dv_pq_bypass == 2) {
memcpy(&cfg, &dv_cfg_bypass, sizeof(struct pq_ctrl_s));
cfg.sharpness0_en = pq_cfg.sharpness0_en;
cfg.sharpness1_en = pq_cfg.sharpness1_en;
} else if (dv_pq_bypass == 1) {
memcpy(&cfg, &dv_cfg_bypass, sizeof(struct pq_ctrl_s));
} else {
@@ -2649,22 +2741,31 @@ int dv_pq_ctl(enum dv_pq_ctl_e ctl)
struct pq_ctrl_s cfg;
switch (ctl) {
case DV_PQ_BYPASS:
case DV_PQ_TV_BYPASS:
memcpy(&cfg, &dv_cfg_bypass, sizeof(struct pq_ctrl_s));
cfg.vadj1_en = pq_cfg.vadj1_en;
vpp_pq_ctrl_config(cfg);
dv_pq_bypass = 2;
pr_amve_dbg("dv enable, pq disable, dv_pq_bypass = %d\n",
vpp_pq_ctrl_config(cfg, WR_DMA);
dv_pq_bypass = 3;
pr_amve_dbg("dv enable, for TV pq disable, dv_pq_bypass = %d\n",
dv_pq_bypass);
break;
case DV_PQ_STB_BYPASS:
memcpy(&cfg, &dv_cfg_bypass, sizeof(struct pq_ctrl_s));
cfg.sharpness0_en = pq_cfg.sharpness0_en;
cfg.sharpness1_en = pq_cfg.sharpness1_en;
vpp_pq_ctrl_config(cfg, WR_DMA);
dv_pq_bypass = 2;
pr_amve_dbg("dv enable, for STB pq disable, dv_pq_bypass = %d\n",
dv_pq_bypass);
break;
case DV_PQ_CERT:
vpp_pq_ctrl_config(dv_cfg_bypass);
vpp_pq_ctrl_config(dv_cfg_bypass, WR_DMA);
dv_pq_bypass = 1;
pr_amve_dbg("dv certification mode, pq disable, dv_pq_bypass = %d\n",
dv_pq_bypass);
break;
case DV_PQ_REC:
vpp_pq_ctrl_config(pq_cfg);
vpp_pq_ctrl_config(pq_cfg, WR_DMA);
dv_pq_bypass = 0;
pr_amve_dbg("dv disable, pq recovery, dv_pq_bypass = %d\n",
dv_pq_bypass);
drivers/media/enhancement/amvecm/amve.h
+1 -1
View File
@@ -223,7 +223,7 @@ void dump_plut3d_reg_table(void);
void amvecm_gamma_init(bool en);
void set_gamma_regs(int en, int sel);
void amvecm_wb_enable(int enable);
int vpp_pq_ctrl_config(struct pq_ctrl_s pq_cfg);
int vpp_pq_ctrl_config(struct pq_ctrl_s pq_cfg, enum wr_md_e md);
unsigned int skip_pq_ctrl_load(struct am_reg_s *p);
void set_pre_gamma_reg(struct pre_gamma_table_s *pre_gma_tb);
void lcd_gamma_api(unsigned int index, u16 *r_data, u16 *g_data,
drivers/media/enhancement/amvecm/amvecm.c
+116 -53
View File
@@ -71,7 +71,7 @@
#include <linux/amlogic/media/amdolbyvision/dolby_vision.h>
#endif
#include "dnlp_cal.h"
#include <linux/amlogic/media/enhancement/amvecm/vlock.h>
#include "vlock.h"
#include "hdr/am_hdr10_plus.h"
#include "local_contrast.h"
#include "arch/vpp_hdr_regs.h"
@@ -323,6 +323,8 @@ unsigned int pd_detect_en;
int pd_weak_fix_lvl = PD_LOW_LVL;
int pd_fix_lvl = PD_HIG_LVL;
unsigned int pd_det;
unsigned int gmv_weak_th = 4;
unsigned int gmv_th = 17;
@@ -1366,6 +1368,10 @@ void amvecm_dejaggy_patch(struct vframe_s *vf)
pd_detect_en = 0;
return;
}
if (!pd_det)
return;
gmv = vf->di_gmv / 10000;
if (vf->height == 1080 &&
@@ -1376,8 +1382,8 @@ void amvecm_dejaggy_patch(struct vframe_s *vf)
return;
pd_detect_en = 1;
pd_combing_fix_patch(pd_fix_lvl);
pr_amvecm_dbg("pd_detect_en1 = %d; level = %d, gmv %d\n",
pd_detect_en, pd_fix_lvl, gmv);
pr_amvecm_dbg("pd_detect_en1 = %d; level = %d, vf->di_pulldown = 0x%x, gmv %d\n",
pd_detect_en, pd_fix_lvl, vf->di_pulldown, gmv);
} else if ((vf->height == 1080) &&
(vf->width == 1920) &&
(vf->di_pulldown & (1 << 3)) &&
@@ -1387,8 +1393,8 @@ void amvecm_dejaggy_patch(struct vframe_s *vf)
pd_detect_en = 2;
pd_combing_fix_patch(pd_weak_fix_lvl);
pr_amvecm_dbg("pd_detect_en2 = %d; level = %d, gmv %d\n",
pd_detect_en, pd_weak_fix_lvl, gmv);
pr_amvecm_dbg("pd_detect_en2 = %d; level = %d, vf->di_pulldown = 0x%x, gmv %d\n",
pd_detect_en, pd_weak_fix_lvl, vf->di_pulldown, gmv);
} else if (pd_detect_en) {
pd_detect_en = 0;
pd_combing_fix_patch(PD_DEF_LVL);
@@ -2842,7 +2848,7 @@ static long amvecm_ioctl(struct file *file,
ret = -EFAULT;
pr_amvecm_dbg("pq control cp pq_ctrl_s fail\n");
} else {
vpp_pq_ctrl_config(pq_cfg);
pq_user_latch_flag |= PQ_USER_PQ_MODULE_CTL;
pr_amvecm_dbg("pq control load success\n");
}
}
@@ -4468,6 +4474,33 @@ static ssize_t amvecm_gamma_show(struct class *cls,
struct class_attribute *attr,
char *buf)
{
int i;
int len = 0;
if (vecm_latch_flag2 & GAMMA_READ_R) {
for (i = 0; i < 256; i++)
len += sprintf(buf + len, "%03x", gamma_data_r[i]);
len += sprintf(buf + len, "\n");
vecm_latch_flag2 &= ~GAMMA_READ_R;
return len;
}
if (vecm_latch_flag2 & GAMMA_READ_G) {
for (i = 0; i < 256; i++)
len += sprintf(buf + len, "%03x", gamma_data_g[i]);
len += sprintf(buf + len, "\n");
vecm_latch_flag2 &= ~GAMMA_READ_G;
return len;
}
if (vecm_latch_flag2 & GAMMA_READ_B) {
for (i = 0; i < 256; i++)
len += sprintf(buf + len, "%03x", gamma_data_b[i]);
len += sprintf(buf + len, "\n");
vecm_latch_flag2 &= ~GAMMA_READ_B;
return len;
}
pr_info("Usage:");
pr_info(" echo sgr|sgg|sgb xxx...xx > /sys/class/amvecm/gamma\n");
pr_info("Notes:\n");
@@ -4490,7 +4523,7 @@ static ssize_t amvecm_gamma_store(struct class *cls,
{
int n = 0;
char *buf_orig, *ps, *token;
char *parm[4];
char *parm[4] = {NULL};
unsigned short *gamma_r, *gamma_g, *gamma_b;
unsigned int gamma_count;
char gamma[4];
@@ -4577,9 +4610,13 @@ static ssize_t amvecm_gamma_store(struct class *cls,
pr_info("gamma_r[%d] = %x\n",
i, gamma_data_r[i]);
} else if (!strcmp(parm[1], "all_str")) {
for (i = 0; i < 256; i++)
d_convert_str(gamma_data_r[i], i, stemp, 3, 16);
pr_info("gamma_r str: %s\n", stemp);
if (!parm[2]) {
for (i = 0; i < 256; i++)
d_convert_str(gamma_data_r[i], i, stemp, 3, 16);
pr_info("gamma_r str: %s\n", stemp);
} else if (!strcmp(parm[2], "adb")) {
vecm_latch_flag2 |= GAMMA_READ_R;
}
} else {
if (kstrtoul(parm[1], 10, &val) < 0) {
pr_info("invalid command\n");
@@ -4589,7 +4626,7 @@ static ssize_t amvecm_gamma_store(struct class *cls,
if (i >= 0 && i <= 255)
pr_info("gamma_r[%d] = %x\n",
i, gamma_data_r[i]);
}
}
} else if (!strcmp(parm[0], "ggg")) {
vpp_get_lcd_gamma_table(H_SEL_G);
if (!strcmp(parm[1], "all")) {
@@ -4597,9 +4634,13 @@ static ssize_t amvecm_gamma_store(struct class *cls,
pr_info("gamma_g[%d] = %x\n",
i, gamma_data_g[i]);
} else if (!strcmp(parm[1], "all_str")) {
for (i = 0; i < 256; i++)
d_convert_str(gamma_data_g[i], i, stemp, 3, 16);
pr_info("gamma_g str: %s\n", stemp);
if (!parm[2]) {
for (i = 0; i < 256; i++)
d_convert_str(gamma_data_g[i], i, stemp, 3, 16);
pr_info("gamma_g str: %s\n", stemp);
} else if (!strcmp(parm[2], "adb")) {
vecm_latch_flag2 |= GAMMA_READ_G;
}
} else {
if (kstrtoul(parm[1], 10, &val) < 0) {
pr_info("invalid command\n");
@@ -4618,9 +4659,13 @@ static ssize_t amvecm_gamma_store(struct class *cls,
pr_info("gamma_b[%d] = %x\n",
i, gamma_data_b[i]);
} else if (!strcmp(parm[1], "all_str")) {
for (i = 0; i < 256; i++)
d_convert_str(gamma_data_b[i], i, stemp, 3, 16);
pr_info("gamma_b str: %s\n", stemp);
if (!parm[2]) {
for (i = 0; i < 256; i++)
d_convert_str(gamma_data_b[i], i, stemp, 3, 16);
pr_info("gamma_b str: %s\n", stemp);
} else if (!strcmp(parm[2], "adb")) {
vecm_latch_flag2 |= GAMMA_READ_B;
}
} else {
if (kstrtoul(parm[1], 10, &val) < 0) {
pr_info("invalid command\n");
@@ -5511,7 +5556,9 @@ static ssize_t amvecm_hdr_tmo_show(struct class *cla,
struct class_attribute *attr, char *buf)
{
hdr10_tmo_parm_show();
return 0;
hdr_tmo_adb_show(buf);
return strlen(buf) + 1;
}
static ssize_t amvecm_hdr_tmo_store(struct class *cla,
@@ -5977,6 +6024,11 @@ void pq_user_latch_process(void)
amvecm_set_saturation_hue(sat_hue_val);
}
if (pq_user_latch_flag & PQ_USER_PQ_MODULE_CTL) {
pq_user_latch_flag &= ~PQ_USER_PQ_MODULE_CTL;
vpp_pq_ctrl_config(pq_cfg, WR_DMA);
}
}
static const char *amvecm_pq_user_usage_str = {
@@ -6425,7 +6477,7 @@ static void amvecm_pq_enable(int enable)
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
if (!is_dolby_vision_enable())
#endif
amcm_enable();
amcm_enable(WR_VCB);
WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE,
1, 1, 1);
WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE,
@@ -6548,7 +6600,7 @@ static void amvecm_pq_enable(int enable)
WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 0, 4, 1);
ve_disable_dnlp();
amcm_disable();
amcm_disable(WR_VCB);
WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE,
0, 1, 1);
@@ -7588,10 +7640,10 @@ static ssize_t amvecm_debug_store(struct class *cla,
}
} else if (!strcmp(parm[0], "cm")) {
if (!strncmp(parm[1], "enable", 6)) {
amcm_enable();
amcm_enable(WR_VCB);
pr_info("enable cm\n");
} else if (!strncmp(parm[1], "disable", 7)) {
amcm_disable();
amcm_disable(WR_VCB);
pr_info("disable cm\n");
} else if (!strcmp(parm[1], "cur_color_md")) {
if (parm[2]) {
@@ -7901,10 +7953,11 @@ static ssize_t amvecm_debug_store(struct class *cla,
unsigned int encode_table_size;
char data[4];
char *buffer = NULL;
#ifdef CONFIG_AMLOGIC_ENABLE_MEDIA_FILE
#ifdef CONFIG_SET_FS
struct file *fp;
mm_segment_t fs;
loff_t pos;
#endif
#endif
encode_table_size =
257 * sizeof(unsigned long);
@@ -7952,13 +8005,15 @@ static ssize_t amvecm_debug_store(struct class *cla,
goto free_buf;
}
#ifdef CONFIG_AMLOGIC_ENABLE_MEDIA_FILE
#ifdef CONFIG_SET_FS
fp = filp_open(parm[3], O_RDONLY, 0);
if (IS_ERR(fp)) {
kfree(section_in);
kfree(buffer);
goto free_buf;
}
//fs = get_fs();
//set_fs(KERNEL_DS);
memset(buffer, 0,
section_len * 9 + encode_table_size);
pos = 0;
@@ -7974,11 +8029,8 @@ static ssize_t amvecm_debug_store(struct class *cla,
goto free_buf;
}
filp_close(fp, NULL);
#else
kfree(section_in);
kfree(buffer);
goto free_buf;
#endif
//set_fs(fs);
#endif
}
if (lut3d_compress) {
huff64_decode(buffer, (unsigned int)readcount,
@@ -8013,10 +8065,11 @@ static ssize_t amvecm_debug_store(struct class *cla,
unsigned int *section_out;
unsigned int encode_table_size;
char *tmp, tmp1[10] = {0};
#ifdef CONFIG_AMLOGIC_ENABLE_MEDIA_FILE
#ifdef CONFIG_SET_FS
struct file *fp;
mm_segment_t fs;
loff_t pos;
#endif
#endif
encode_table_size =
257 * sizeof(unsigned long);
@@ -8081,7 +8134,7 @@ static ssize_t amvecm_debug_store(struct class *cla,
}
if (parm[3]) {
#ifdef CONFIG_AMLOGIC_ENABLE_MEDIA_FILE
#ifdef CONFIG_SET_FS
fp = filp_open(parm[3],
O_RDWR | O_CREAT | O_APPEND,
0644);
@@ -8090,17 +8143,16 @@ static ssize_t amvecm_debug_store(struct class *cla,
kfree(tmp);
goto free_buf;
}
//fs = get_fs();
//set_fs(KERNEL_DS);
pos = fp->f_pos;
vfs_write(fp, tmp,
len,
&pos);
filp_close(fp, NULL);
#else
kfree(section_out);
kfree(tmp);
goto free_buf;
#endif
//set_fs(fs);
#endif
}
kfree(section_out);
@@ -8308,6 +8360,13 @@ static ssize_t amvecm_debug_store(struct class *cla,
pr_info("hist sel: Y hist\n");
}
}
} else if (!strcmp(parm[0], "pd_det")) {
if (parm[1]) {
if (kstrtoul(parm[1], 10, &val) < 0)
goto free_buf;
}
pd_det = (uint)val;
pr_info("pd_det: %d\n", pd_det);
} else {
pr_info("unsupport cmd\n");
}
@@ -9293,19 +9352,19 @@ static void def_hdr_sdr_mode(void)
void hdr_hist_config_int(void)
{
VSYNC_WRITE_VPP_REG(VD1_HDR2_HIST_CTRL, 0x5510);
VSYNC_WRITE_VPP_REG(VD1_HDR2_HIST_H_START_END, 0x10000);
VSYNC_WRITE_VPP_REG(VD1_HDR2_HIST_V_START_END, 0x0);
WRITE_VPP_REG(VD1_HDR2_HIST_CTRL, 0x5510);
WRITE_VPP_REG(VD1_HDR2_HIST_H_START_END, 0x10000);
WRITE_VPP_REG(VD1_HDR2_HIST_V_START_END, 0x0);
if (get_cpu_type() != MESON_CPU_MAJOR_ID_T5 &&
get_cpu_type() != MESON_CPU_MAJOR_ID_T5D) {
VSYNC_WRITE_VPP_REG(VD2_HDR2_HIST_CTRL, 0x5510);
VSYNC_WRITE_VPP_REG(VD2_HDR2_HIST_H_START_END, 0x10000);
VSYNC_WRITE_VPP_REG(VD2_HDR2_HIST_V_START_END, 0x0);
WRITE_VPP_REG(VD2_HDR2_HIST_CTRL, 0x5510);
WRITE_VPP_REG(VD2_HDR2_HIST_H_START_END, 0x10000);
WRITE_VPP_REG(VD2_HDR2_HIST_V_START_END, 0x0);
VSYNC_WRITE_VPP_REG(OSD1_HDR2_HIST_CTRL, 0x5510);
VSYNC_WRITE_VPP_REG(OSD1_HDR2_HIST_H_START_END, 0x10000);
VSYNC_WRITE_VPP_REG(OSD1_HDR2_HIST_V_START_END, 0x0);
WRITE_VPP_REG(OSD1_HDR2_HIST_CTRL, 0x5510);
WRITE_VPP_REG(OSD1_HDR2_HIST_H_START_END, 0x10000);
WRITE_VPP_REG(OSD1_HDR2_HIST_V_START_END, 0x0);
}
}
@@ -9391,7 +9450,9 @@ void init_pq_setting(void)
/*kernel sdr2hdr match uboot setting*/
def_hdr_sdr_mode();
vpp_pq_ctrl_config(pq_cfg);
vpp_pq_ctrl_config(pq_cfg, WR_VCB);
pq_reg_wr_rdma = 1;
}
return;
@@ -9432,7 +9493,7 @@ tvchip_pq_setting:
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1);
else
VSYNC_WRITE_VPP_REG(VPP_VADJ_CTRL, 0xd);
WRITE_VPP_REG(VPP_VADJ_CTRL, 0xd);
/*probe close sr0 peaking for switch on video*/
WRITE_VPP_REG_BITS(VPP_SRSHARP0_CTRL, 1, 0, 1);
@@ -9471,7 +9532,9 @@ tvchip_pq_setting:
/*dnlp alg parameters init*/
dnlp_alg_param_init();
vpp_pq_ctrl_config(pq_cfg);
vpp_pq_ctrl_config(pq_cfg, WR_VCB);
pq_reg_wr_rdma = 1;
}
/* #endif*/
@@ -10021,9 +10084,9 @@ static void aml_vecm_dt_parse(struct platform_device *pdev)
#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
if (!is_dolby_vision_enable())
#endif
amcm_enable();
amcm_enable(WR_VCB);
} else {
amcm_disable();
amcm_disable(WR_VCB);
}
/* WRITE_VPP_REG_BITS(VPP_MISC, cm_en, 28, 1); */
@@ -10273,7 +10336,7 @@ static void amvecm_shutdown(struct platform_device *pdev)
hdr_exit();
ve_disable_dnlp();
amcm_disable();
amcm_disable(WR_VCB);
WRITE_VPP_REG(VPP_VADJ_CTRL, 0x0);
amvecm_wb_enable(0);
/*dnlp cm vadj1 wb gate*/
drivers/media/enhancement/amvecm/frame_lock_policy.c
+1 -1
View File
@@ -14,7 +14,7 @@
#include <linux/amlogic/media/vout/vout_notify.h>
#include "reg_helper.h"
#include "frame_lock_policy.h"
#include "vlock.h"
#define FrameLockPR(fmt, args...) pr_info("FrameLock: " fmt "", ## args)
#define FrameLockERR(fmt, args...) pr_err("FrameLock ERR: " fmt "", ## args)
drivers/media/enhancement/amvecm/hdr/am_hdr10_tmo_fw.c
+125
View File
@@ -231,6 +231,131 @@ void hdr10_tmo_reg_get(struct hdr_tmo_sw *pre_tmo_reg_s)
pre_tmo_reg_s->alpha = tmo_reg.alpha;
}
static char hdr_tmo_debug_usage_str[33][25] = {
"tmo_en = ",
"reg_highlight = ",
"reg_light_th = ",
"reg_hist_th = ",
"reg_highlight_th1 = ",
"reg_highlight_th2 = ",
"reg_display_e = ",
"reg_middle_a = ",
"reg_middle_a_adj = ",
"reg_middle_b = ",
"reg_middle_s = ",
"reg_max_th1 = ",
"reg_middle_th = ",
"reg_thold2 = ",
"reg_thold3 = ",
"reg_thold4 = ",
"reg_thold1 = ",
"reg_max_th2 = ",
"reg_pnum_th = ",
"reg_hl0 = ",
"reg_hl1 = ",
"reg_hl2 = ",
"reg_hl3 = ",
"reg_display_adj = ",
"reg_low_adj = ",
"reg_high_en = ",
"reg_high_adj1 = ",
"reg_high_adj2 = ",
"reg_high_maxdiff = ",
"reg_high_mindiff = ",
"reg_avg_th = ",
"reg_avg_adj = ",
"alpha = "
};
void hdr10_tmo_reg_get_arr(int *arry)
{
arry[0] = tmo_reg.tmo_en;
arry[1] = tmo_reg.reg_highlight;
arry[2] = tmo_reg.reg_light_th;
arry[3] = tmo_reg.reg_hist_th;
arry[4] = tmo_reg.reg_highlight_th1;
arry[5] = tmo_reg.reg_highlight_th2;
arry[6] = tmo_reg.reg_display_e;
arry[7] = tmo_reg.reg_middle_a;
arry[8] = tmo_reg.reg_middle_a_adj;
arry[9] = tmo_reg.reg_middle_b;
arry[10] = tmo_reg.reg_middle_s;
arry[11] = tmo_reg.reg_max_th1;
arry[12] = tmo_reg.reg_middle_th;
arry[13] = tmo_reg.reg_thold2;
arry[14] = tmo_reg.reg_thold3;
arry[15] = tmo_reg.reg_thold4;
arry[16] = tmo_reg.reg_thold1;
arry[17] = tmo_reg.reg_max_th2;
arry[18] = tmo_reg.reg_pnum_th;
arry[19] = tmo_reg.reg_hl0;
arry[20] = tmo_reg.reg_hl1;
arry[21] = tmo_reg.reg_hl2;
arry[22] = tmo_reg.reg_hl3;
arry[23] = tmo_reg.reg_display_adj;
arry[24] = tmo_reg.reg_low_adj;
arry[25] = tmo_reg.reg_high_en;
arry[26] = tmo_reg.reg_high_adj1;
arry[27] = tmo_reg.reg_high_adj2;
arry[28] = tmo_reg.reg_high_maxdiff;
arry[29] = tmo_reg.reg_high_mindiff;
arry[30] = tmo_reg.reg_avg_th;
arry[31] = tmo_reg.reg_avg_adj;
arry[32] = tmo_reg.alpha;
}
static int arry_int2str(int val, char *str_tmp)
{
int temp;
char str[10];
int len = 0, count = 0;
if (val == 0) {
str_tmp[count++] = '0';
return count;
}
while (val) {
temp = val % 10;
str[len++] = temp + '0';
val /= 10;
}
str[len] = '\0';
while (len) {
str_tmp[count++] = str[len - 1];
len--;
}
str_tmp[count] = '\0';
return count;
}
void hdr_tmo_adb_show(char *str)
{
int tmo_val[33];
int i = 0, j = 0, k = 0;
int len1 = 0, len2 = 0;
char str_tmp[25];
hdr10_tmo_reg_get_arr(tmo_val);
for (i = 0; i < 33; i++) {
len1 = strlen(hdr_tmo_debug_usage_str[i]);
for (k = 0; k < len1; k++) {
/*copy str from hdr_tmo_debug_usage_str*/
str[j++] = hdr_tmo_debug_usage_str[i][k];
}
len2 = arry_int2str(tmo_val[i], str_tmp);
for (k = 0; k < len2; k++) {
/*copy tmo_val*/
str[j++] = str_tmp[k];
}
str[j++] = '\n';
}
str[j] = '\0';
}
struct aml_tmo_reg_sw *tmo_fw_param_get(void)
{
return &tmo_reg;
drivers/media/enhancement/amvecm/hdr/am_hdr10_tmo_fw.h
+1
View File
@@ -10,4 +10,5 @@ int hdr10_tmo_dbg(char **param);
void hdr10_tmo_parm_show(void);
void hdr10_tmo_reg_set(struct hdr_tmo_sw *pre_tmo_reg);
void hdr10_tmo_reg_get(struct hdr_tmo_sw *pre_tmo_reg_s);
void hdr_tmo_adb_show(char *str);
drivers/media/enhancement/amvecm/hdr/gamut_convert.c
+1
View File
@@ -416,6 +416,7 @@ int gamut_convert_process(struct vinfo_s *vinfo,
}
} else if ((source_type[vd_path] == HDRTYPE_HDR10) ||
(source_type[vd_path] == HDRTYPE_HLG) ||
(source_type[vd_path] == HDRTYPE_PRIMESL) ||
(source_type[vd_path] == HDRTYPE_HDR10PLUS)) {
if (get_primary_policy() == PRIMARIES_AUTO) {
for (i = 0; i < 3; i++)
drivers/media/enhancement/amvecm/reg_helper.h
+9
View File
@@ -214,6 +214,11 @@ static inline u32 READ_VPP_REG_BITS(u32 reg,
#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
WRITE_VPP_REG_BITS(adr, val, start, len)
#define _VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define _VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)
#define _VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
WRITE_VPP_REG_BITS(adr, val, start, len)
#define VSYNC_WR_MPEG_REG_VPP1(adr, val) WRITE_VCBUS_REG(adr, val)
#define VSYNC_RD_MPEG_REG_VPP1(adr) READ_VCBUS_REG(adr)
#define VSYNC_WR_MPEG_REG_BITS_VPP1(adr, val, start, len) \
@@ -233,6 +238,10 @@ int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
u32 VSYNC_RD_MPEG_REG(u32 adr);
int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
int _VSYNC_WR_MPEG_REG(u32 adr, u32 val);
int _VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
u32 _VSYNC_RD_MPEG_REG(u32 adr);
int VSYNC_WR_MPEG_REG_BITS_VPP1(u32 adr, u32 val, u32 start, u32 len);
u32 VSYNC_RD_MPEG_REG_VPP1(u32 adr);
int VSYNC_WR_MPEG_REG_VPP1(u32 adr, u32 val);
drivers/media/enhancement/amvecm/set_hdr2_v0.c
+8 -4
View File
@@ -1153,7 +1153,8 @@ void set_hdr_matrix(enum hdr_module_sel module_sel,
int vpp_sel;
if (vpp_index == VPP_TOP1 &&
get_cpu_type() == MESON_CPU_MAJOR_ID_T7)
(get_cpu_type() == MESON_CPU_MAJOR_ID_T7 ||
get_cpu_type() == MESON_CPU_MAJOR_ID_T3))
vpp_sel = VPP_TOP1;
else if (vpp_index == VPP_TOP2 &&
get_cpu_type() == MESON_CPU_MAJOR_ID_T7)
@@ -2753,7 +2754,8 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel,
if (((module_sel == OSD1_HDR && vpp_index == VPP_TOP1) ||
(module_sel == OSD3_HDR && vpp_index == VPP_TOP0)) &&
get_cpu_type() == MESON_CPU_MAJOR_ID_T7) {
(get_cpu_type() == MESON_CPU_MAJOR_ID_T7 ||
get_cpu_type() == MESON_CPU_MAJOR_ID_T3)) {
pr_csc(12, "%s: module_sel = %d vpp_index = %d not match\n",
__func__, module_sel, vpp_index);
return hdr_process_select;
@@ -2766,7 +2768,8 @@ enum hdr_process_sel hdr_func(enum hdr_module_sel module_sel,
vpp_index);
if (vpp_index == VPP_TOP1 &&
get_cpu_type() == MESON_CPU_MAJOR_ID_T7)
(get_cpu_type() == MESON_CPU_MAJOR_ID_T7 ||
get_cpu_type() == MESON_CPU_MAJOR_ID_T3))
vpp_sel = VPP_TOP1;
else if (vpp_index == VPP_TOP2 &&
get_cpu_type() == MESON_CPU_MAJOR_ID_T7)
@@ -3958,7 +3961,8 @@ void mtx_setting(enum vpp_matrix_e mtx_sel,
get_cpu_type() == MESON_CPU_MAJOR_ID_T7)
vpp_sel = VPP_TOP2;
else if (mtx_sel == VPP1_POST2_MTX &&
get_cpu_type() == MESON_CPU_MAJOR_ID_T7)
(get_cpu_type() == MESON_CPU_MAJOR_ID_T7 ||
get_cpu_type() == MESON_CPU_MAJOR_ID_T3))
vpp_sel = VPP_TOP1;
else
vpp_sel = VPP_TOP0;
drivers/media/enhancement/amvecm/vlock.c
+51 -11
View File
@@ -34,11 +34,12 @@
#include <linux/amlogic/media/vout/lcd/lcd_notify.h>
#endif
#include "arch/vpp_regs.h"
#include <linux/amlogic/media/enhancement/amvecm/vlock.h>
#include "vlock.h"
#include "amvecm_vlock_regmap.h"
#include "amcm.h"
#include "reg_helper.h"
#include <linux/amlogic/gki_module.h>
#include "frame_lock_policy.h"
/* video lock */
/* 0:off;
@@ -72,7 +73,7 @@ static unsigned int vlock_intput_type;
*/
static signed int vlock_line_limit = 2;
static signed int vlock_enc_maxtune_line_num = 8;
static signed int vlock_enc_maxtune_line_num = 12;
module_param(vlock_enc_maxtune_line_num, uint, 0664);
MODULE_PARM_DESC(vlock_enc_maxtune_line_num, "\n vlock_enc_maxtune_line_num\n");
@@ -190,6 +191,9 @@ u32 loop0_en = 2; /*0:off, 1:on 2:auto*/
u32 loop1_en = 1; /*0:off, 1:on 2:auto*/
u32 speed_up_en = 1;
static int vlock_protect_min;
static int vlock_manual;
struct reg_map vlock_reg_maps[REG_MAP_END] = {0};
struct vlk_reg_map_tab regmap_tab_tm2[] = {
@@ -474,7 +478,7 @@ int __attribute__((weak))frc_is_on(void)
return 0;
}
static void vlock_tune_sync_frc(u32 frc_vporch_cal)
static void vlock_tune_sync_frc(u32 frc_vporch_cal, unsigned char frc_s2l_en)
{
u32 max_lncnt;
u32 max_pxcnt;
@@ -487,11 +491,15 @@ static void vlock_tune_sync_frc(u32 frc_vporch_cal)
frc_vporch_cal : (max_lncnt - 1950);
if ((vlock_debug & VLOCK_DEBUG_FLASH))
pr_info("vlock: %s max_lncnt =%d max_pxcnt =%d frc_v_porch =%d\n",
pr_info("vlock: %s max_lncnt =%d max_pxcnt =%d frc_v_porch =%d frc_s2l_en=%d\n",
__func__,
max_lncnt, max_pxcnt, frc_v_porch);
max_lncnt, max_pxcnt, frc_v_porch, frc_s2l_en);
if (frc_s2l_en)
WRITE_VPP_REG(ENCL_SYNC_TO_LINE_EN, (1 << 13) | (max_lncnt - frc_v_porch));
else
WRITE_VPP_REG_BITS(ENCL_SYNC_TO_LINE_EN, 0, 13, 1);
WRITE_VPP_REG(ENCL_SYNC_TO_LINE_EN, (1 << 13) | (max_lncnt - frc_v_porch));
WRITE_VPP_REG(ENCL_SYNC_PIXEL_EN, (1 << 15) | (max_pxcnt - 1));
WRITE_VPP_REG(ENCL_SYNC_LINE_LENGTH, max_lncnt - frc_v_porch - 1);
}
@@ -530,6 +538,7 @@ int vlock_sync_frc_vporch(struct stvlock_frc_param frc_param)
if (!pvlock)
return ret;
vlock_manual = frc_param.frc_mcfixlines;
if (pvlock->dtdata->vlk_ctl_for_frc) {
if (pvlock->fsm_sts == VLOCK_STATE_ENABLE_STEP1_DONE ||
pvlock->fsm_sts == VLOCK_STATE_ENABLE_STEP2_DONE) {
@@ -540,12 +549,12 @@ int vlock_sync_frc_vporch(struct stvlock_frc_param frc_param)
ret = 0;
} else {
pr_info("vlock: vlock is NULL or Disable, frc set max lncnt and ma px cnt!");
vlock_tune_sync_frc(frc_param.frc_v_porch);
vlock_tune_sync_frc(frc_param.frc_v_porch, frc_param.s2l_en);
ret = 0;
}
} else {
pr_info("vlock: vlk_ctl_for_frc = 0 no need vlock avoid flash patch!!!");
vlock_tune_sync_frc(frc_param.frc_v_porch);
vlock_tune_sync_frc(frc_param.frc_v_porch, frc_param.s2l_en);
ret = 0;
}
@@ -1231,6 +1240,18 @@ void vlock_vmode_check(struct stvlock_sig_sts *pvlock)
}
}
static void vlock_lock_status_check(struct stvlock_sig_sts *pvlock)
{
if (vlock_get_phlock_flag() && vlock_get_vlock_flag()) {
if (vlock_debug & VLOCK_DEBUG_PROTECT)
pr_info("vlock locked success !!!\n");
} else {
if (vlock_debug & VLOCK_DEBUG_PROTECT)
pr_info("vlock locking fsm_sts=%d\n",
pvlock->fsm_sts);
}
}
static void vlock_disable_step1(struct stvlock_sig_sts *pvlock)
{
unsigned int m_reg_value, tmp_value;
@@ -1555,7 +1576,11 @@ static void vlock_enable_step3_enc(struct stvlock_sig_sts *pvlock)
}
if (enc_max_pixel > 0x1fff)
enc_max_line += 1;
WRITE_VPP_REG(pvlock->enc_max_line_addr + offset_enc, enc_max_line);
if (enc_max_line >= vlock_protect_min)
WRITE_VPP_REG(pvlock->enc_max_line_addr + offset_enc, enc_max_line);
else if ((vlock_debug & VLOCK_DEBUG_FLASH))
pr_info("vlock:WARNING... enc_max_line:%d is limited by prt_min:%d cannot adj contiue\n",
enc_max_line, vlock_protect_min);
if ((vlock_debug & VLOCK_DEBUG_FLASH)) {
pr_info("polity_line_num=%d line_num=%d, org_line=%d\n",
polity_line_num, line_num, pvlock->org_enc_line_num);
@@ -2010,8 +2035,8 @@ void vlock_enable_step3_auto_enc(struct stvlock_sig_sts *pvlock)
stbdec_win0 = READ_VPP_REG(VPU_VLOCK_STBDET_WIN0_WIN1 + offset_vlck) & 0xff;
stbdec_win1 = (READ_VPP_REG(VPU_VLOCK_STBDET_WIN0_WIN1 + offset_vlck) >> 8) & 0xff;
th0 = (oa * stbdec_win0 * 7) / vinfo->vtotal;
th1 = (oa * stbdec_win1 * 8) / vinfo->vtotal;
th0 = (oa * stbdec_win0 * 10) / vinfo->vtotal;
th1 = (oa * stbdec_win1 * 10) / vinfo->vtotal;
WRITE_VPP_REG(VPU_VLOCK_WIN0_TH + offset_vlck, th0);
WRITE_VPP_REG(VPU_VLOCK_WIN1_TH + offset_vlck, th1);
@@ -2484,6 +2509,7 @@ u32 vlock_fsm_input_check(struct stvlock_sig_sts *pvlock, struct vframe_s *vf)
vframe_sts = true;
vlock_vmode_check(pvlock);
vlock_lock_status_check(pvlock);
if (vf) {
vinfo = get_current_vinfo();
@@ -2494,6 +2520,12 @@ u32 vlock_fsm_input_check(struct stvlock_sig_sts *pvlock, struct vframe_s *vf)
pvlock->duration = vf->duration;
//if (vlock_debug & VLOCK_DEBUG_INFO)
// pr_info("input_hz:%d duration:%d\n", pvlock->input_hz, pvlock->duration);
vlock_protect_min =
vinfo->vbp + vinfo->vsw + vinfo->height + vlock_manual;
if (vlock_debug & VLOCK_DEBUG_PROTECT)
pr_info("prt_min:%d org_enc_line_num:%d vbp:%d vsw:%d height:%d vlock_manual:%d\n",
vlock_protect_min, pvlock->org_enc_line_num,
vinfo->vbp, vinfo->vsw, vinfo->height, vlock_manual);
}
/*check vf exist status*/
@@ -3195,6 +3227,7 @@ void vlock_status(struct stvlock_sig_sts *pvlock)
pr_info("lcnt_sts :0x%0x\n", pvlock->vdinsts.lcnt_sts);
pr_info("com_sts0 :0x%0x\n", pvlock->vdinsts.com_sts0);
pr_info("com_sts1 :0x%0x\n", pvlock->vdinsts.com_sts1);
pr_info("vlock_protect_min:%d\n", vlock_protect_min);
}
void vlock_reg_dump(struct stvlock_sig_sts *pvlock)
@@ -3492,6 +3525,8 @@ ssize_t vlock_debug_show(struct class *cla,
"echo log_stop > /sys/class/amvecm/vlock\n");
len += sprintf(buf + len,
"echo log_print > /sys/class/amvecm/vlock\n");
len += sprintf(buf + len,
"echo vlock_protect > /sys/class/amvecm/vlock\n");
return len;
}
@@ -3677,6 +3712,11 @@ ssize_t vlock_debug_store(struct class *cla,
return -EINVAL;
loop1_en = val;
pr_info("loop1_en:%d\n", loop1_en);
} else if (!strncmp(parm[0], "vlock_manual", 12)) {
if (kstrtol(parm[1], 10, &val) < 0)
return -EINVAL;
vlock_manual = val;
pr_info("vlock_manual:%d\n", vlock_manual);
} else {
pr_info("----cmd list -----\n");
pr_info("vlock_mode val\n");
drivers/media/enhancement/amvecm/vlock.h
+4 -3
View File
@@ -24,9 +24,7 @@
#include <linux/amlogic/media/vfm/vframe.h>
#include "linux/amlogic/media/amvecm/ve.h"
//Ref.2021/1118: chg frc set max line to vlock module
#define VLOCK_VER "Ref.2021/1207: hdmi black screen low probility"
#define VLOCK_VER "Ref.2022/0425: fix vlock log cost long time"
#define VLOCK_REG_NUM 33
#define VLOCK_ALL_LOCK_CNT 400
@@ -191,6 +189,8 @@ struct stvlock_frc_param {
u32 max_lncnt;
u32 max_pxcnt;
u32 frc_v_porch;
u32 frc_mcfixlines;
unsigned char s2l_en;
};
#define diff(a, b) ({ \
@@ -305,6 +305,7 @@ enum vlock_pll_sel {
#define VLOCK_DEBUG_FSM_PAUSE (0x40)
#define VLOCK_DEBUG_FORCE_ON (0x80)
#define VLOCK_DEBUG_FLASH (0x100)
#define VLOCK_DEBUG_PROTECT (0x200)
#define VLOCK_DEBUG_INFO_ERR (BIT(15))
drivers/media/frc/Makefile
+1 -1
View File
@@ -20,4 +20,4 @@ $(MEDIA_MODULE_NAME)-$(CONFIG_AMLOGIC_MEDIA_FRC) += frc/frc_hw.o
# $(MEDIA_MODULE_NAME)-$(CONFIG_AMLOGIC_MEDIA_FRC) += frc/frc_mc.o
# $(MEDIA_MODULE_NAME)-$(CONFIG_AMLOGIC_MEDIA_FRC) += frc/frc_phase_table.o
ccflags-y += -I$(srctree)/$(COMMON_DRIVERS_DIR)/drivers/media/enhancement/amvecm
drivers/media/frc/frc_hw.c
+1 -1
View File
@@ -35,7 +35,7 @@
#include <linux/amlogic/media/frc/frc_reg.h>
#include <linux/amlogic/media/amvecm/amvecm.h>
// #include <linux/amlogic/media/frc/frc_common.h>
#include "vlock.h"
#include "frc_drv.h"
#include "frc_hw.h"
#include "frc_regs_table.h"
include/linux/amlogic/media/amvecm/amvecm.h
+12 -3
View File
@@ -30,7 +30,6 @@
#include <linux/amlogic/media/registers/cpu_version.h>
#include <linux/amlogic/media/video_sink/vpp.h>
#include <drm/drmP.h>
#include <linux/amlogic/media/enhancement/amvecm/vlock.h>
#ifndef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION
bool is_dolby_vision_enable(void);
@@ -108,7 +107,9 @@ void dolby_vision_set_toggle_flag(int flag);
*#define VPP_VADJ1_BLMINUS_EN (1 << 1)
*#define VPP_VADJ1_EN (1 << 0)
*/
#define GAMMA_READ_B BIT(10)
#define GAMMA_READ_G BIT(9)
#define GAMMA_READ_R BIT(8)
#define VPP_EYE_PROTECT_UPDATE BIT(7)
#define VPP_PRE_GAMMA_UPDATE BIT(6)
#define VPP_MARTIX_GET BIT(5)
@@ -119,6 +120,7 @@ void dolby_vision_set_toggle_flag(int flag);
#define VPP_DEMO_CM_EN BIT(0)
/*PQ USER LATCH*/
#define PQ_USER_PQ_MODULE_CTL BIT(26)
#define PQ_USER_OVERSCAN_RESET BIT(25)
#define PQ_USER_CMS_SAT_HUE BIT(24)
#define PQ_USER_CMS_CURVE_HUE_HS BIT(23)
@@ -178,11 +180,17 @@ enum cm_hist_e {
};
enum dv_pq_ctl_e {
DV_PQ_BYPASS = 0,
DV_PQ_TV_BYPASS = 0,
DV_PQ_STB_BYPASS,
DV_PQ_CERT,
DV_PQ_REC,
};
enum wr_md_e {
WR_VCB = 0,
WR_DMA,
};
enum pq_table_name_e {
TABLE_NAME_SHARPNESS0 = 0x1,/*in vpp*/
TABLE_NAME_SHARPNESS1 = 0x2,/*in vpp*/
@@ -457,6 +465,7 @@ enum hdr_type_e {
HDRTYPE_HDR10PLUS = HDR10PLUS_SOURCE,
HDRTYPE_DOVI = DOVI_SOURCE,
HDRTYPE_MVC = MVC_SOURCE,
HDRTYPE_PRIMESL = PRIMESL_SOURCE,
};
enum pd_comb_fix_lvl_e {
include/linux/amlogic/media/enhancement/amvecm/vlock.h
-359
View File
@@ -1,359 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* drivers/amlogic/media/enhancement/amvecm/vlock.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __AM_VLOCK_H
#define __AM_VLOCK_H
#include <linux/notifier.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/amlogic/media/vfm/vframe.h>
#include "linux/amlogic/media/amvecm/ve.h"
//Ref.2021/1118: chg frc set max line to vlock module
#define VLOCK_VER "Ref.2021/1207: hdmi black screen low probility"
#define VLOCK_REG_NUM 33
#define VLOCK_ALL_LOCK_CNT 400
struct vdin_sts {
unsigned int lcnt_sts;
unsigned int com_sts0;
unsigned int com_sts1;
};
struct vlock_log_s {
unsigned int pll_m;
unsigned int pll_frac;
signed int line_num_adj;
unsigned int enc_line_max;
signed int pixel_num_adj;
unsigned int enc_pixel_max;
signed int T0;
signed int vdif_err;
signed int err_sum;
signed int margin;
unsigned int vlock_regs[VLOCK_REG_NUM];
};
struct reg_map {
unsigned int phy_addr;
unsigned int size;
void __iomem *p;
};
enum vlock_regmap_e {
REG_MAP_VPU = 0,
REG_MAP_HIU,
REG_MAP_ANACTRL,/*enc*/
REG_MAP_END,
};
enum vlock_src_in_e {
VLOCK_SRC_UNUSE = 0,
VLOCK_SRC_HDMI = 1,
VLOCK_SRC_TV_DEC = 2,
VLOCK_SRC_DVIN0 = 3,
VLOCK_SRC_DVIN1 = 4,
VLOCK_SRC_BT656 = 5,
};
enum vlock_out_goes_e {
VLOCK_OUT_ENCL = 0,
VLOCK_OUT_ENCP = 1,
VLOCK_OUT_ENCI = 2,
};
enum vlock_enc_num_e {
VLOCK_ENC0 = 0,
VLOCK_ENC1,
VLOCK_ENC2,
VLOCK_ENC_MAX,
};
//#define VLOCK_DEBUG_ENC_IDX VLOCK_ENC2
struct vlk_reg_map_tab {
unsigned int base;
unsigned int size;
};
enum vlock_param_e {
VLOCK_EN = 0x0,
VLOCK_ADAPT,
VLOCK_MODE,
VLOCK_DIS_CNT_LIMIT,
VLOCK_DELTA_LIMIT,
VLOCK_PLL_M_LIMIT,
VLOCK_DELTA_CNT_LIMIT,
VLOCK_DEBUG,
VLOCK_DYNAMIC_ADJUST,
VLOCK_STATE,
VLOCK_SYNC_LIMIT_FLAG,
VLOCK_DIS_CNT_NO_VF_LIMIT,
VLOCK_LINE_LIMIT,
VLOCK_SUPPORT,
VLOCK_PARAM_MAX,
};
struct stvlock_sig_sts {
u32 fsm_sts;
u32 fsm_prests;
u32 fsm_pause;
u32 vf_sts;
u32 vmd_chg;
u32 frame_cnt_in;
u32 frame_cnt_no;
u32 input_hz;
u32 duration;
u32 output_hz;
bool md_support;
u32 video_inverse;
u32 phlock_percent;
u32 phlock_sts;
u32 phlock_en;
u32 phlock_cnt;
u32 frqlock_sts;
/*u32 frqlock_stable_cnt;*/
u32 ss_sts;
u32 pll_mode_pause;
struct vecm_match_data_s *dtdata;
u32 val_frac;
u32 val_m;
struct vdin_sts vdinsts;
u32 start_chk_ph;
u32 all_lock_cnt;
enum vlock_enc_num_e idx;
u32 offset_encl; /*enc0,enc1,enc2 address offset*/
u32 offset_vlck; /*vlock0,vlock1,vlock2 address offset*/
u32 m_update_cnt;
u32 f_update_cnt;
u32 enable_cnt;
u32 enable_auto_enc_cnt;
/*monitor*/
u32 pre_line;
u32 pre_pixel;
/*check lock sts*/
u32 chk_lock_sts_rstflag;
u32 chk_lock_sts_cnt;
u32 chk_lock_sts_vs_in;
u32 chk_lock_sts_vs_out;
u32 hhi_pll_reg_m;
u32 hhi_pll_reg_frac;
u32 pre_hiu_reg_m;
u32 pre_hiu_reg_frac;
u32 enc_max_line_addr;
u32 enc_max_pixel_addr;
u32 pre_enc_max_pixel;
u32 pre_enc_max_line;
u32 org_enc_line_num;
u32 org_enc_pixel_num;
u32 enc_video_mode_addr;
u32 enc_video_mode_adv_addr;
u32 enc_max_line_switch_addr;
u32 enc_frc_v_porch_addr;
u32 enc_frc_v_porch;
u32 enc_frc_max_line;
u32 enc_frc_max_pixel;
u32 last_i_vsync;
u32 err_accum;
};
enum vlock_change {
VLOCK_CHG_NONE = 0,
VLOCK_CHG_PH_UNCLOCK,
VLOCK_CHG_NEED_RESET,
};
struct stvlock_frc_param {
u32 max_lncnt;
u32 max_pxcnt;
u32 frc_v_porch;
};
#define diff(a, b) ({ \
typeof(a) _a = a; \
typeof(b) _b = b; \
(((_a) > (_b)) ? ((_a) - (_b)) : ((_b) - (_a))); })
//void amve_vlock_process(struct vframe_s *vf);
//void amve_vlock_resume(void);
void vlock_param_set(unsigned int val, enum vlock_param_e sel);
void vlock_status(struct stvlock_sig_sts *pvlock);
void vlock_reg_dump(struct stvlock_sig_sts *pvlock);
void vlock_log_start(void);
void vlock_log_stop(void);
void vlock_log_print(void);
#define VLOCK_STATE_NULL 0
#define VLOCK_STATE_ENABLE_STEP1_DONE 1
#define VLOCK_STATE_ENABLE_STEP2_DONE 2
#define VLOCK_STATE_DISABLE_STEP1_DONE 3
#define VLOCK_STATE_DISABLE_STEP2_DONE 4
#define VLOCK_STATE_ENABLE_FORCE_RESET 5
/* video lock */
enum VLOCK_MD {
VLOCK_MODE_AUTO_ENC = 0x01,
VLOCK_MODE_AUTO_PLL = 0x02,
VLOCK_MODE_MANUAL_PLL = 0x04,
VLOCK_MODE_MANUAL_ENC = 0x08,
VLOCK_MODE_MANUAL_SOFT_ENC = 0x10,
VLOCK_MODE_MANUAL_MIX_PLL_ENC = 0x20,
};
/* ------------------ reg ----------------------*/
/*base 0xfe008000*/
#define ANACTRL_TCON_PLL_VLOCK (0x00f2 << 2)
#define ANACTRL_TCON_PLL0_CNTL0 (0x00e0 << 2)/*M(7:0) N(14:10)*/
#define ANACTRL_TCON_PLL0_CNTL1 (0x00e1 << 2)/*frac(18:0)*/
#define ANACTRL_TCON_PLL1_CNTL0 (0x00e5 << 2)
#define ANACTRL_TCON_PLL1_CNTL1 (0x00e6 << 2)
#define ANACTRL_TCON_PLL2_CNTL0 (0x00ea << 2)
#define ANACTRL_TCON_PLL2_CNTL1 (0x00eb << 2)
/* ------------------ reg ----------------------*/
#define IS_MANUAL_MODE(md) ((md) & \
(VLOCK_MODE_MANUAL_PLL | \
VLOCK_MODE_MANUAL_ENC | \
VLOCK_MODE_MANUAL_SOFT_ENC))
#define IS_AUTO_MODE(md) ((md) & \
(VLOCK_MODE_AUTO_PLL | \
VLOCK_MODE_AUTO_ENC))
#define IS_PLL_MODE(md) ((md) & \
(VLOCK_MODE_MANUAL_PLL | \
VLOCK_MODE_AUTO_PLL))
#define IS_ENC_MODE(md) ((md) & \
(VLOCK_MODE_MANUAL_ENC | \
VLOCK_MODE_MANUAL_SOFT_ENC | \
VLOCK_MODE_AUTO_ENC))
#define IS_AUTO_PLL_MODE(md) ((md) & \
VLOCK_MODE_AUTO_PLL)
#define IS_AUTO_ENC_MODE(md) ((md) & \
VLOCK_MODE_AUTO_ENC)
#define IS_MANUAL_ENC_MODE(md) ((md) & \
VLOCK_MODE_MANUAL_ENC)
#define IS_MANUAL_PLL_MODE(md) ((md) & \
VLOCK_MODE_MANUAL_PLL)
#define IS_MANUAL_SOFTENC_MODE(md) ((md) & \
VLOCK_MODE_MANUAL_SOFT_ENC)
enum vlock_pll_sel {
vlock_pll_sel_tcon = 0,
vlock_pll_sel_hdmi,
vlock_pll_sel_disable = 0xf,
};
#define VLOCK_START_CNT 2
#define VLOCK_UPDATE_M_CNT 2
#define VLOCK_UPDATE_F_CNT 2
#define XTAL_VLOCK_CLOCK 24000000/*vlock use xtal clock*/
#define VLOCK_SUPPORT_HDMI BIT(0)
#define VLOCK_SUPPORT_CVBS BIT(1)
/*25 to 50, 30 to 60*/
#define VLOCK_SUPPORT_1TO2 0x4
#define VLOCK_SUP_MODE (VLOCK_SUPPORT_HDMI | VLOCK_SUPPORT_CVBS | \
VLOCK_SUPPORT_1TO2)
/*10s for 60hz input,vlock pll stabel cnt limit*/
#define VLOCK_PLL_STABLE_LIMIT 600
#define VLOCK_ENC_STABLE_CNT 180/*vlock enc stabel cnt limit*/
#define VLOCK_PLL_ADJ_LIMIT 9/*vlock pll adj limit(0x300a default)*/
/*vlock_debug mask*/
#define VLOCK_DEBUG_INFO (0x1)
#define VLOCK_DEBUG_FLUSH_REG_DIS (0x2)
#define VLOCK_DEBUG_ENC_LINE_ADJ_DIS (0x4)
#define VLOCK_DEBUG_ENC_PIXEL_ADJ_DIS (0x8)
#define VLOCK_DEBUG_AUTO_MODE_LOG_EN (0x10)
#define VLOCK_DEBUG_PLL2ENC_DIS (0x20)
#define VLOCK_DEBUG_FSM_PAUSE (0x40)
#define VLOCK_DEBUG_FORCE_ON (0x80)
#define VLOCK_DEBUG_FLASH (0x100)
#define VLOCK_DEBUG_INFO_ERR (BIT(15))
#define ENCL_SYNC_LINE_LENGTH 0x1c4c
#define ENCL_SYNC_PIXEL_EN 0x1c4d
#define ENCL_SYNC_TO_LINE_EN 0x1c4e
#define ENCL_FRC_CTRL 0x1cdd
/* 0:enc;1:pll;2:manual pll */
extern unsigned int vlock_mode;
extern unsigned int vlock_en;
extern unsigned int vecm_latch_flag;
/*extern void __iomem *amvecm_hiu_reg_base;*/
extern unsigned int probe_ok;
extern u32 phase_en_after_frqlock;
extern u32 vlock_ss_en;
void lcd_ss_enable(bool flag);
unsigned int lcd_ss_status(void);
int amvecm_hiu_reg_read(unsigned int reg, unsigned int *val);
int amvecm_hiu_reg_write(unsigned int reg, unsigned int val);
void vdin_vlock_input_sel(struct stvlock_sig_sts *vlock, unsigned int type,
enum vframe_source_type_e source_type);
void vlock_param_config(struct device_node *node);
#ifdef CONFIG_AMLOGIC_LCD
extern struct work_struct aml_lcd_vlock_param_work;
void vlock_lcd_param_work(struct work_struct *p_work);
void lcd_vlock_m_update(int index, unsigned int vlock_m);
void lcd_vlock_frac_update(int index, unsigned int vlock_frac);
#endif
int vlock_notify_callback(struct notifier_block *block,
unsigned long cmd, void *para);
#endif
void vlock_status_init(void);
void vlock_dt_match_init(struct vecm_match_data_s *pdata);
void vlock_set_en(bool en);
void vlock_set_phase(struct stvlock_sig_sts *vlock, u32 percent);
void vlock_set_phase_en(struct stvlock_sig_sts *vlock, u32 en);
int lcd_set_ss(unsigned int level, unsigned int freq, unsigned int mode);
ssize_t vlock_debug_store(struct class *cla,
struct class_attribute *attr,
const char *buf, size_t count);
ssize_t vlock_debug_show(struct class *cla,
struct class_attribute *attr, char *buf);
void vlock_clk_config(struct device *dev);
int frc_is_on(void);
bool vlock_get_phlock_flag(void);
bool vlock_get_vlock_flag(void);
int vlock_sync_frc_vporch(struct stvlock_frc_param frc_param);
void vlock_set_sts_by_frame_lock(bool en);