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ddr_bandwidth: ddr theoretic max bandwidth value error [1/1]

Browse Source 
PD#SWPL-109664

Problem:
ddr theoretic max bandwidth value error

Solution:
some soc dmc bus bandwidth is 16

Verify:
s5

Change-Id: I233c6ba840f4a758bd0b7335fde5cca436ae41a6
Signed-off-by: qinglin.li <qinglin.li@amlogic.com>
This commit is contained in:
qinglin.li
2023-02-01 19:52:57 +08:00
parent 144e7e1030
commit 330c0722c7
2 changed files with 9 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/memory_debug/ddr_tool/ddr_band_op_t7.c
+1 -5
View File
@@ -203,11 +203,7 @@ static unsigned long t7_get_dmc_freq_quick(struct ddr_bandwidth *db)
od1 = (((val >> 19) & 0x1)) == 1 ? 2 : 1;
freq = DEFAULT_XTAL_FREQ / 1000; /* avoid overflow */
if (n) {
if (db->cpu_type == DMC_TYPE_P1)
freq = ((((freq * m) / n) >> od1) / od_div) * 1000 / 2;
else
freq = ((((freq * m) / n) >> od1) / od_div) * 1000;
freq = ((((freq * m) / n) >> od1) / od_div) * 1000;
}
return freq;
drivers/memory_debug/ddr_tool/ddr_bandwidth.c
+8 -1
View File
@@ -181,7 +181,14 @@ static void cal_ddr_usage(struct ddr_bandwidth *db, struct ddr_grant *dg)
}
} else {
mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number;
/* ddr data bus width = dmc bus width * dmc number.
* After s4 soc, not register to distinguish ddr data bus width,
* default ereryone dmc bus width is 32, but p1 and s5 is 16.
*/
if (db->cpu_type == DMC_TYPE_P1 || db->cpu_type == DMC_TYPE_S5)
mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number / 2;
else
mbw = (u64)freq * db->bytes_per_cycle * db->dmc_number;
}
if (!mbw) {
pr_emerg("warning: theoretic max bandwidth is zer0\n");