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gpu: s6 use devfreq policy [1/1]

Browse Source 
PD#SWPL-173296

Problem:
enable s6 gpu dfs function

Solution:
s6 use devfreq policy

Verify:
s6

Change-Id: I7f041eb2f4bd1acc5971f17887cc8199bf7d33d7
Signed-off-by: Yongjie Zhu <yongjie.zhu@amlogic.com>
This commit is contained in:
Yongjie Zhu
2024-06-15 09:51:13 +00:00
committed by Luan Yuan
parent fa8c304417
commit 45a4bf1995
2 changed files with 36 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm64/boot/dts/amlogic/meson-s6.dtsi
+26 -3
View File
@@ -2340,10 +2340,30 @@
gpu_opp_table: gpu_opp_table {
compatible = "operating-points-v2";
opp-285 {
opp-hz = /bits/ 64 <285714281>;
opp-microvolt = <1150>;
};
opp-400 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150>;
};
opp-500 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1150>;
};
opp-666 {
opp-hz = /bits/ 64 <666666666>;
opp-microvolt = <1150>;
};
opp-800 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1150>;
};
opp-996 {
opp-hz = /bits/ 64 <996000000>;
opp-microvolt = <1150>;
};
};
};
@@ -3329,19 +3349,22 @@
<&clkc CLKID_MALI>,
<&clkc CLKID_MALI_STACK_0_MUX>,
<&clkc CLKID_MALI_STACK_0>,
<&clkc CLKID_MALI_STACK>; /* Glitch free mux */
<&clkc CLKID_MALI_STACK>, /* Glitch free mux */
<&scmi_clk CLKID_GP1_PLL>;
assigned-clock-parents = <&clkc CLKID_FCLK_DIV5>,
<0>, /* Do Nothing */
<&clkc CLKID_MALI_0>,
<&clkc CLKID_FCLK_DIV5>,
<0>,
<&clkc CLKID_MALI_STACK_0>;
<&clkc CLKID_MALI_STACK_0>,
<0>;
assigned-clock-rates = <0>, /* Do Nothing */
<400000000>,
<0>,
<0>,
<400000000>,
<0>; /* Do Nothing */
<0>, /* Do Nothing */
<996000000>;
tbl = <&dvfs400_cfg>;//bringup s6 use fix clock 400M
arch/arm64/boot/dts/amlogic/meson-valhall.dtsi
+10
View File
@@ -118,6 +118,16 @@
keep_count = <5>;
threshold = <80 255>;
};
dvfs996_cfg:dvfs996_cfg {
clk_freq = <996000000>;
clk_parent = "gp1_pll";
clkp_freq = <996000000>;
clk_reg = <0x200>;
voltage = <1150>;
keep_count = <5>;
threshold = <80 255>;
};
};
};/* end of / */