mirror of
https://github.com/hardkernel/kernel_common_drivers.git
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Audio: add ad82120b driver support [2/2]
PD#SWPL-182569 Problem: need to support ad82120b driver Solution: add ad82120b driver Verify: use T6d Change-Id: I04ad5d64af2241dc5b7e051afa0052f5153b8238 Signed-off-by: jiebing chen <jiebing.chen@amlogic.com>
This commit is contained in:
jiebing chen
committed by
gerrit autosubmit
gerrit autosubmit
parent
585f2d92f4
commit
60550567f3
@@ -533,6 +533,7 @@
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compatible = "amlogic, auge-sound-card";
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aml-audio-card,name = "AML-AUGESOUND";
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avout_mute-gpios = <&gpio GPIOD_6 GPIO_ACTIVE_HIGH>;
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spk_mute-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_LOW>;
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spk_mute_sleep_time = <800>;
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@@ -1192,12 +1193,12 @@
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins1>;
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clock-frequency = <300000>;
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ad82128: ad82128@6c {
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compatible = "ESMT,ad82128";
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ad82120b: ad82120b@6c {
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compatible = "ESMT,ad82120b";
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#sound-dai-cells = <0>;
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//reset_pin-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
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reset_pin-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
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reg = <0x6c>;
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status = "okay";
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status = "disabled";
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};
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};
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@@ -533,6 +533,7 @@
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compatible = "amlogic, auge-sound-card";
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aml-audio-card,name = "AML-AUGESOUND";
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avout_mute-gpios = <&gpio GPIOD_6 GPIO_ACTIVE_HIGH>;
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spk_mute-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_LOW>;
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spk_mute_sleep_time = <800>;
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@@ -597,7 +598,7 @@
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};
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tdmbcodec: codec {
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prefix-names = "AMP";
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sound-dai = </*&ad82128*/ &acodec>;
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sound-dai = </*&ad82120b*/ &acodec>;
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};
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};
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@@ -1161,12 +1162,12 @@
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins1>;
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clock-frequency = <300000>;
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ad82128: ad82128@6c {
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compatible = "ESMT,ad82128";
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ad82120b: ad82120b@6c {
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compatible = "ESMT,ad82120b";
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#sound-dai-cells = <0>;
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//reset_pin-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
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reset_pin-gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
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reg = <0x6c>;
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status = "okay";
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status = "disabled";
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};
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};
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@@ -545,7 +545,7 @@
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avout_mute-gpios = <&gpio GPIOD_6 GPIO_ACTIVE_HIGH>;
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/* headphone insert det */
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// aml-audio-card,hp-det-gpio = <&analog_gpio CDAC_IOUT GPIO_ACTIVE_LOW>;
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aml-audio-card,hp-det-gpio = <&gpio_analog CDAC_IOUT GPIO_ACTIVE_LOW>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "audio_exception64";
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@@ -543,12 +543,10 @@
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auge_sound {
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compatible = "amlogic, auge-sound-card";
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aml-audio-card,name = "AML-AUGESOUND";
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avout_mute-gpios = <&gpio GPIOD_6 GPIO_ACTIVE_HIGH>;
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/* headphone insert det */
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// aml-audio-card,hp-det-gpio = <&analog_gpio CDAC_IOUT GPIO_ACTIVE_LOW>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>;
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aml-audio-card,hp-det-gpio = <&gpio_analog CDAC_IOUT GPIO_ACTIVE_LOW>;
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interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "audio_exception64";
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aml-audio-card,dai-link@0 {
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@@ -415,6 +415,9 @@ CONFIG_AMLOGIC_SND_CODEC_TL1_ACODEC=m
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#amlogic-snd-codec-t6d.ko
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CONFIG_AMLOGIC_SND_CODEC_T6D_ACODEC=m
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#snd-soc-ad82120b.ko
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CONFIG_AMLOGIC_SND_SOC_AD82120B=m
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# snd-soc-tas5805.ko
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CONFIG_AMLOGIC_SND_SOC_TAS5805=m
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@@ -423,6 +426,10 @@ CONFIG_AMLOGIC_SND_SOC_PA1=m
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#snd-soc-AD82128.ko
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CONFIG_AMLOGIC_SND_SOC_AD82128=m
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# amlogic-snd-codec-tas5707.ko
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CONFIG_AMLOGIC_SND_SOC_TAS5707=m
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# amlogic-usb ko
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CONFIG_AMLOGIC_USB=y
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CONFIG_AMLOGIC_USB_SUPPORT=m
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@@ -254,6 +254,17 @@ config AMLOGIC_SND_SOC_AD82584F
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Enable Support for ESMT AD82584f CODEC.
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Select this if your AD82584F is connected via an I2C bus.
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config AMLOGIC_SND_SOC_AD82120B
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tristate "ESMT AD82120B"
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depends on AMLOGIC_SND_SOC_CODECS
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depends on I2C
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default n
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help
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Enable Support for ESMT AD82120B CODEC.
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Select this if your AD82120B is connected via an I2C bus.
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Enable Support for ESMT AD82120B CODEC.
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Select this if your AD82120B is connected via an I2C bus.
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config AMLOGIC_SND_SOC_CS42528
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tristate "Cirrus Logic CS42528"
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depends on AMLOGIC_SND_SOC_CODECS
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@@ -95,3 +95,10 @@ PR_FMT_DEFINE_SY6026L = "-Dpr_fmt(fmt)= \"[$(PR_FMT_SY6026L)]: \" fmt"
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obj-$(CONFIG_AMLOGIC_SND_SOC_SY6026L) += $(MODULE_NAME_SY6026L).o
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CFLAGS_SY6026L.o += $(PR_FMT_DEFINE_SY6026L)
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$(MODULE_NAME_SY6026L)-y += sy602x.o
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MODULE_NAME_AD82120B = amlogic-snd-codec-ad82120b
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PR_FMT_AD82120B = $(subst amlogic-,,$(MODULE_NAME_AD82120B))
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PR_FMT_DEFINE_AD82120B = "-Dpr_fmt(fmt)= \"[$(PR_FMT_AD82120B)]: \" fmt"
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obj-$(CONFIG_AMLOGIC_SND_SOC_AD82120B) += $(MODULE_NAME_AD82120B).o
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CFLAGS_ad82120b.o += $(PR_FMT_DEFINE_AD82120B)
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$(MODULE_NAME_AD82120B)-y += ad82120b.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __AD82120B_H__
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#define __AD82120B_H__
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#define AD82120B_REGISTER_COUNT 166
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#define AD82120B_RAM1_TABLE_COUNT 162
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#define AD82120B_RAM2_TABLE_COUNT 159
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/* Register Address Map */
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#define AD82120B_STATE_CTRL1_REG 0x00
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#define AD82120B_STATE_CTRL2_REG 0x01
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#define AD82120B_STATE_CTRL3_REG 0x02
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#define AD82120B_VOLUME_CTRL_REG 0x03
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#define AD82120B_STATE_CTRL4_REG 0x0C
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#define AD82120B_STATE_CTRL5_REG 0x1A
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#define CFADDR 0x1d
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#define A1CF1 0x1e
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#define A1CF2 0x1f
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#define A1CF3 0x20
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#define A1CF4 0x21
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#define CFUD 0x32
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#define AD82120B_DEVICE_ID_REG 0x37
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#define AD82120B_CLK_DET_CTRL 0x56
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#define AD82120B_FAULT_REG 0x4D
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#define AD82120B_MAX_REG 0xA5
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/* AD82120B_STATE_CTRL2_REG */
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#define AD82120B_SSZ_DS BIT(5)
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/* AD82120B_STATE_CTRL1_REG */
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#define AD82120B_SAIF_I2S (0x0 << 5)
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#define AD82120B_SAIF_LEFTJ (0x1 << 5)
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#define AD82120B_SAIF_FORMAT_MASK GENMASK(7, 5)
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/* AD82120B_STATE_CTRL3_REG */
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#define AD82120B_MUTE BIT(6)
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/* AD82120B_STATE_CTRL5_REG */
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#define AD82120B_SW_RESET BIT(5)
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/* AD82120B_CLK_DET_CTRL */
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#define AD82120B_ASR_DET BIT(7)
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/* AD82120B_DEVICE_ID_REG */
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#define AD82120B_DEVICE_ID 0xA0
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/* AD82120B_STATE_CTRL4_REG */
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#define AD82120B_CHIP_SYNC_EN BIT(1)
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/* AD82120B_FAULT_REG */
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#define AD82120B_OCE BIT(7)
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#define AD82120B_OTE BIT(6)
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#define AD82120B_UVE BIT(5)
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#define AD82120B_DCDE BIT(4)
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#define AD82120B_BSUVE BIT(3)
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#define AD82120B_CLKE BIT(2)
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#define AD82120B_OVPE BIT(1)
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#define AD82120B_D_CLKE BIT(0)
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#endif /* __AD82120B_H__ */
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@@ -0,0 +1,510 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#if DEBUG_0
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static unsigned char eq_mode_1_reg_tab[AD82120B_REGISTER_COUNT][2] = {
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{0x00, 0x00}, //##State_Control_1
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{0x01, 0x82}, //##State_Control_2
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{0x02, 0x00}, //##State_Control_3
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{0x03, 0x40}, //##Master_volume_control
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{0x04, 0x18}, //##Channel_1_volume_control
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{0x05, 0x18}, //##Channel_2_volume_control
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{0x06, 0x18}, //##Channel_3_volume_control
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{0x07, 0x18}, //##Channel_4_volume_control
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{0x08, 0x18}, //##Channel_5_volume_control
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{0x09, 0x18}, //##Channel_6_volume_control
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{0x0A, 0x40}, //##DTC_Setting
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{0x0B, 0x00}, //##Reserve
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{0x0C, 0x90}, //##State_Control_4
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{0x0D, 0x80}, //##Channel_1_configuration_registers
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{0x0E, 0x80}, //##Channel_2_configuration_registers
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{0x0F, 0x80}, //##Channel_3_configuration_registers
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{0x10, 0x80}, //##Channel_4_configuration_registers
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{0x11, 0x80}, //##Channel_5_configuration_registers
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{0x12, 0x80}, //##Channel_6_configuration_registers
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{0x13, 0x80}, //##Channel_7_configuration_registers
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{0x14, 0x80}, //##Channel_8_configuration_registers
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{0x15, 0x00}, //##Reserve
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{0x16, 0x00}, //##Reserve
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{0x17, 0x00}, //##Reserve
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{0x18, 0x00}, //##Reserve
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{0x19, 0x80}, //##Reserve
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{0x1A, 0x28}, //##State_Control_5
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{0x1B, 0x80}, //##State_Control_6
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{0x1C, 0x20}, //##State_Control_7
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{0x1D, 0x00}, //##Coefficient_RAM_Base_Address
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{0x1E, 0x00}, //##First_4-bits_of_coefficients_A1
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{0x1F, 0x00}, //##Second_8-bits_of_coefficients_A1
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{0x20, 0x00}, //##Third_8-bits_of_coefficients_A1
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{0x21, 0x00}, //##Fourth-bits_of_coefficients_A1
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{0x22, 0x00}, //##First_4-bits_of_coefficients_A2
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{0x23, 0x00}, //##Second_8-bits_of_coefficients_A2
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{0x24, 0x00}, //##Third_8-bits_of_coefficients_A2
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{0x25, 0x00}, //##Fourth_8-bits_of_coefficients_A2
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{0x26, 0x00}, //##First_4-bits_of_coefficients_B1
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{0x27, 0x00}, //##Second_8-bits_of_coefficients_B1
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{0x28, 0x00}, //##Third_8-bits_of_coefficients_B1
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{0x29, 0x00}, //##Fourth_8-bits_of_coefficients_B1
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{0x2A, 0x00}, //##First_4-bits_of_coefficients_B2
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{0x2B, 0x00}, //##Second_8-bits_of_coefficients_B2
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{0x2C, 0x00}, //##Third_8-bits_of_coefficients_B2
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{0x2D, 0x00}, //##Fourth-bits_of_coefficients_B2
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{0x2E, 0x00}, //##First_4-bits_of_coefficients_A0
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{0x2F, 0x80}, //##Second_8-bits_of_coefficients_A0
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{0x30, 0x00}, //##Third_8-bits_of_coefficients_A0
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{0x31, 0x00}, //##Fourth_8-bits_of_coefficients_A0
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{0x32, 0x00}, //##Coefficient_RAM_R/W_control
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{0x33, 0x02}, //##State_Control_8
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{0x34, 0x00}, //##Reserve
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{0x35, 0x00}, //##Volume_Fine_tune
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{0x36, 0x00}, //##Volume_Fine_tune
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{0x37, 0xA0}, //##Device_ID_register
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{0x38, 0x00}, //##Level_Meter_Clear
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{0x39, 0x00}, //##Power_Meter_Clear
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{0x3A, 0x00}, //##First_8bits_of_C1_Level_Meter
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{0x3B, 0x00}, //##Second_8bits_of_C1_Level_Meter
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{0x3C, 0x00}, //##Third_8bits_of_C1_Level_Meter
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{0x3D, 0x00}, //##Fourth_8bits_of_C1_Level_Meter
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{0x3E, 0x00}, //##First_8bits_of_C2_Level_Meter
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{0x3F, 0x00}, //##Second_8bits_of_C2_Level_Meter
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{0x40, 0x00}, //##Third_8bits_of_C2_Level_Meter
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{0x41, 0x00}, //##Fourth_8bits_of_C2_Level_Meter
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{0x42, 0x00}, //##CHK_stat
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{0x43, 0x00}, //##First_4_bits_of_BEQ_CHK_val
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{0x44, 0x00}, //##Second_8_bits_of_BEQ_CHK_val
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{0x45, 0x00}, //##Third_4_bits_of_BEQ_CHK_val
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{0x46, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_val
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{0x47, 0x00}, //##First_4_bits_of_BEQ_CHK_result
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{0x48, 0x00}, //##Second_4_bits_of_BEQ_CHK_result
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{0x49, 0x00}, //##Third_4_bits_of_BEQ_CHK_result
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{0x4A, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_result
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{0x4B, 0x10}, //##digital_DC_control
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{0x4C, 0x20}, //##digital_DC_judge_threshold
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{0x4D, 0xFF}, //##ERROR_register
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{0x4E, 0xFF}, //##ERROR_latch_register
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{0x4F, 0x00}, //##ERROR_clear_register
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{0x50, 0x01}, //##ERROR_register_2
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{0x51, 0x01}, //##ERROR_latch_register_2
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{0x52, 0x00}, //##ERROR_clear_register_2
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{0x53, 0x00}, //##Reserve
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{0x54, 0x00}, //##Reserve
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{0x55, 0x20}, //##clock_FS_detection
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{0x56, 0x10}, //##CLK_DET
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{0x57, 0x00}, //##TDM_word_width_selection
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{0x58, 0x00}, //##TDM_offset
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{0x59, 0x06}, //##I2S_Data_output_selection_register
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{0x5A, 0x08}, //##PWM_frequency_selection
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{0x5B, 0x00}, //##Mono_Key_High_Byte
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{0x5C, 0x00}, //##Mono_Key_Low_Byte
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{0x5D, 0x07}, //##Hi-res_Item
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{0x5E, 0x00}, //##analog_gain
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{0x5F, 0x00}, //##AGC_Control
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{0x60, 0x00}, //##Channel1_EQ_bypass_1
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{0x61, 0x00}, //##Channel1_EQ_bypass_2
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{0x62, 0x00}, //##Channel1_EQ_bypass_3
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{0x63, 0x00}, //##Channel2_EQ_bypass_1
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{0x64, 0x00}, //##Channel2_EQ_bypass_2
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{0x65, 0x00}, //##Channel2_EQ_bypass_3
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{0x66, 0x00}, //##ATTACK_HOLD_SET
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{0x67, 0x00}, //##Reserve
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{0x68, 0x00}, //##Reserve
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{0x69, 0x00}, //##Reserve
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{0x6A, 0x00}, //##Reserve
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{0x6B, 0x00}, //##Reserve
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{0x6C, 0x02}, //##FS_and_PMF_read_out
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{0x6D, 0x03}, //##OC_Selection
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{0x6E, 0x00}, //##digital_DC_control_testmode
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{0x6F, 0x32}, //##test_mode_register0
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{0x70, 0x07}, //##noise_gate_analog_gain
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{0x71, 0x41}, //##Testmode_register1
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{0x72, 0x38}, //##Testmode_register2
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{0x73, 0x18}, //##dither_signal_setting
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{0x74, 0x0D}, //##Error_Delay
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{0x75, 0x05}, //##First_4bits_of_MBIST_User_Program_Even
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{0x76, 0x55}, //##Second_8bits_of_MBIST_User_Program_Even
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{0x77, 0x55}, //##Third_8bits_of_MBIST_User_Program_Even
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{0x78, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Even
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{0x79, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Even
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{0x7A, 0x05}, //##First_8bits_of_MBIST_User_Program_Odd
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{0x7B, 0x55}, //##Second_8bits_of_MBIST_User_Program_Odd
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{0x7C, 0x55}, //##Third_8bits_of_MBIST_User_Program_Odd
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{0x7D, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Odd
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{0x7E, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Odd
|
||||
{0x7F, 0x50}, //##IP_shutdown_register
|
||||
{0x80, 0x00}, //##Protection_Register_Set
|
||||
{0x81, 0x00}, //##MBIST_Status
|
||||
{0x82, 0x00}, //##PWM_output_control
|
||||
{0x83, 0x00}, //##Test_Mode_Control
|
||||
{0x84, 0x00}, //##RAM1_test_register_address
|
||||
{0x85, 0x00}, //##First_4bits_of_RAM1_data
|
||||
{0x86, 0x00}, //##Second_8bits_of_RAM1_Data
|
||||
{0x87, 0x00}, //##Third_8bits_of_RAM1_data
|
||||
{0x88, 0x00}, //##Fourth_8bits_of_RAM1_Data
|
||||
{0x89, 0x00}, //##Fifth_8bits_of_RAM1_Data
|
||||
{0x8A, 0x00}, //##RAM1_test_r/w_control
|
||||
{0x8B, 0x00}, //##RAM2_test_register_address
|
||||
{0x8C, 0x00}, //##First_4bits_of_RAM2_data
|
||||
{0x8D, 0x00}, //##Second_8bits_of_RAM2_Data
|
||||
{0x8E, 0x00}, //##Third_8bits_of_RAM2_data
|
||||
{0x8F, 0x00}, //##Fourth_8bits_of_RAM2_Data
|
||||
{0x90, 0x00}, //##Fifth_8bits_of_RAM2_Data
|
||||
{0x91, 0x00}, //##RAM2_test_r/w_control
|
||||
{0x92, 0x00}, //##BURN_EN1
|
||||
{0x93, 0x00}, //##BURN_EN2
|
||||
{0x94, 0x00}, //##OSC_TRIM_CTRL
|
||||
{0x95, 0x80}, //##PLL_CTRL
|
||||
{0x96, 0x11}, //##PLL_CTRL2
|
||||
{0x97, 0x06}, //##CLKDET_read_out1
|
||||
{0x98, 0x11}, //##CLKDET_read_out2
|
||||
{0x99, 0x02}, //##CLKDET_read_out3
|
||||
{0x9A, 0x56}, //##CLKDET_read_out4
|
||||
{0x9B, 0x90}, //##CLKDET_read_out5
|
||||
{0x9C, 0x3F}, //##CLKDET_read_out6
|
||||
{0x9D, 0x00}, //##CLKDET_read_out7
|
||||
{0x9E, 0x02}, //##CLKDET_read_out8
|
||||
{0x9F, 0x02}, //##RECOUNT_CTRL
|
||||
{0xA0, 0xE4}, //##RECOUNT_STABLE_CTRL
|
||||
{0xA1, 0x04}, //##Auto_clock_detect_FS96k_window
|
||||
{0xA2, 0x04}, //##Auto_clock_detect_FS48k_window
|
||||
{0xA3, 0x04}, //##Auto_clock_detect_FS16k_window
|
||||
{0xA4, 0x04}, //##Auto_clock_detect_FS8k_window
|
||||
{0xA5, 0x80}, //##SYNC_LR
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef AD82120B_CHANGE_EQ_MODE_EN
|
||||
//###################RAM1_Table {RAM1 Address, Top Byte Of RAM1 Data ,
|
||||
//Middle Byte Of RAM1 Data , Botton Byte Of RAM1 Data }####################
|
||||
static unsigned char eq_mode_1_ram1_tab[][5] = {
|
||||
{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ1
|
||||
{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ1
|
||||
{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ1
|
||||
{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ1
|
||||
{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ1
|
||||
{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ2
|
||||
{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ2
|
||||
{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ2
|
||||
{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ2
|
||||
{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ2
|
||||
{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ3
|
||||
{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ3
|
||||
{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ3
|
||||
{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ3
|
||||
{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ3
|
||||
{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ4
|
||||
{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ4
|
||||
{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ4
|
||||
{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ4
|
||||
{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ4
|
||||
{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ5
|
||||
{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ5
|
||||
{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ5
|
||||
{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ5
|
||||
{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ5
|
||||
{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ6
|
||||
{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ6
|
||||
{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ6
|
||||
{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ6
|
||||
{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ6
|
||||
{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ7
|
||||
{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ7
|
||||
{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ7
|
||||
{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ7
|
||||
{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ7
|
||||
{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ8
|
||||
{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ8
|
||||
{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ8
|
||||
{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ8
|
||||
{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ8
|
||||
{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ9
|
||||
{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ9
|
||||
{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ9
|
||||
{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ9
|
||||
{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ9
|
||||
{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ10
|
||||
{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ10
|
||||
{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ10
|
||||
{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ10
|
||||
{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ10
|
||||
{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ11
|
||||
{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ11
|
||||
{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ11
|
||||
{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ11
|
||||
{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ11
|
||||
{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ12
|
||||
{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ12
|
||||
{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ12
|
||||
{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ12
|
||||
{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ12
|
||||
{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ13
|
||||
{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ13
|
||||
{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ13
|
||||
{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ13
|
||||
{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ13
|
||||
{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ14
|
||||
{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ14
|
||||
{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ14
|
||||
{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ14
|
||||
{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ14
|
||||
{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ15
|
||||
{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ15
|
||||
{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ15
|
||||
{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ15
|
||||
{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ15
|
||||
{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ16
|
||||
{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ16
|
||||
{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ16
|
||||
{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ16
|
||||
{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ16
|
||||
{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ17
|
||||
{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ17
|
||||
{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ17
|
||||
{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ17
|
||||
{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ17
|
||||
{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ18
|
||||
{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ18
|
||||
{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ18
|
||||
{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ18
|
||||
{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ18
|
||||
{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ19
|
||||
{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ19
|
||||
{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ19
|
||||
{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ19
|
||||
{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ19
|
||||
{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ20
|
||||
{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ20
|
||||
{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ20
|
||||
{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ20
|
||||
{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ20
|
||||
{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ21
|
||||
{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ21
|
||||
{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ21
|
||||
{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ21
|
||||
{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ21
|
||||
{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ22
|
||||
{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ22
|
||||
{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ22
|
||||
{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ22
|
||||
{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ22
|
||||
{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ23
|
||||
{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ23
|
||||
{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ23
|
||||
{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ23
|
||||
{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ23
|
||||
{0x73, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_1_Mixer1
|
||||
{0x74, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_Mixer2
|
||||
{0x75, 0x00, 0x7E, 0x88, 0xE0}, //##Channel_1_Prescale
|
||||
{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_Postscale
|
||||
{0x77, 0x02, 0x00, 0x00, 0x00}, //##CH1.2_Power_Clipping
|
||||
{0x78, 0x00, 0x00, 0x01, 0xA0}, //####Noise_Gate_Attack_Level
|
||||
{0x79, 0x00, 0x00, 0x05, 0x30}, //##Noise_Gate_Release_Level
|
||||
{0x7A, 0x00, 0x01, 0x00, 0x00}, //##DRC1_Energy_Coefficient
|
||||
{0x7B, 0x00, 0x01, 0x00, 0x00}, //##DRC2_Energy_Coefficient
|
||||
{0x7C, 0x00, 0x01, 0x00, 0x00}, //##DRC3_Energy_Coefficient
|
||||
{0x7D, 0x00, 0x01, 0x00, 0x00}, //##DRC4_Energy_Coefficient
|
||||
{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC1_Power_Meter
|
||||
{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC3_Power_Meter
|
||||
{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC5_Power_Meter
|
||||
{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC7_Power_Meter
|
||||
{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN1
|
||||
{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN2
|
||||
{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN3
|
||||
{0x85, 0x0E, 0x01, 0xC0, 0x70}, //##DRC1_FF_threshold
|
||||
{0x86, 0x02, 0x00, 0x00, 0x00}, //##DRC1_FF_slope
|
||||
{0x87, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_aa
|
||||
{0x88, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_da
|
||||
{0x89, 0x0E, 0x01, 0xC0, 0x70}, //##DRC2_FF_threshold
|
||||
{0x8A, 0x02, 0x00, 0x00, 0x00}, //##DRC2_FF_slope
|
||||
{0x8B, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_aa
|
||||
{0x8C, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_da
|
||||
{0x8D, 0x0E, 0x01, 0xC0, 0x70}, //##DRC3_FF_threshold
|
||||
{0x8E, 0x02, 0x00, 0x00, 0x00}, //##DRC3_FF_slope
|
||||
{0x8F, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_aa
|
||||
{0x90, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_da
|
||||
{0x91, 0x0E, 0x01, 0xC0, 0x70}, //##DRC4_FF_threshold
|
||||
{0x92, 0x02, 0x00, 0x00, 0x00}, //##DRC4_FF_slope
|
||||
{0x93, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_aa
|
||||
{0x94, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_da
|
||||
{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_LCH_GAIN
|
||||
{0x9A, 0x02, 0x00, 0x00, 0x00}, //##SRS_Gain
|
||||
{0x9B, 0x01, 0xD7, 0xE6, 0xE0}, //##Compensate_A0
|
||||
{0x9C, 0x00, 0x2E, 0x77, 0x40}, //##Compensate_A1
|
||||
{0x9D, 0x0F, 0xF9, 0xA1, 0xE0}, //##Compensate_B1
|
||||
{0x9E, 0x01, 0x91, 0x2B, 0xE0}, //##QT_AT
|
||||
{0x9F, 0x01, 0x1B, 0x5A, 0xB9}, //##QT_RT
|
||||
{0xA0, 0x00, 0x5F, 0xCA, 0xCA}, //##QT_Region_T
|
||||
{0xA1, 0x00, 0x00, 0x00, 0x00}, //##QT_Region_B
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SND_SOC_AD82120B_2CHANNEL
|
||||
//###################RAM2_Table {RAM2 Address, Top Byte Of RAM2 Data ,
|
||||
//Middle Byte Of RAM2 Data , Botton Byte Of RAM2 Data }####################
|
||||
static unsigned char eq_mode_1_ram2_tab[][5] = {
|
||||
{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ1
|
||||
{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ1
|
||||
{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ1
|
||||
{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ1
|
||||
{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ1
|
||||
{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ2
|
||||
{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ2
|
||||
{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ2
|
||||
{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ2
|
||||
{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ2
|
||||
{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ3
|
||||
{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ3
|
||||
{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ3
|
||||
{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ3
|
||||
{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ3
|
||||
{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ4
|
||||
{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ4
|
||||
{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ4
|
||||
{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ4
|
||||
{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ4
|
||||
{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ5
|
||||
{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ5
|
||||
{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ5
|
||||
{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ5
|
||||
{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ5
|
||||
{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ6
|
||||
{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ6
|
||||
{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ6
|
||||
{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ6
|
||||
{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ6
|
||||
{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ7
|
||||
{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ7
|
||||
{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ7
|
||||
{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ7
|
||||
{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ7
|
||||
{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ8
|
||||
{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ8
|
||||
{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ8
|
||||
{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ8
|
||||
{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ8
|
||||
{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ9
|
||||
{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ9
|
||||
{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ9
|
||||
{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ9
|
||||
{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ9
|
||||
{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ10
|
||||
{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ10
|
||||
{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ10
|
||||
{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ10
|
||||
{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ10
|
||||
{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ11
|
||||
{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ11
|
||||
{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ11
|
||||
{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ11
|
||||
{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ11
|
||||
{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ12
|
||||
{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ12
|
||||
{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ12
|
||||
{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ12
|
||||
{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ12
|
||||
{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ13
|
||||
{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ13
|
||||
{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ13
|
||||
{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ13
|
||||
{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ13
|
||||
{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ14
|
||||
{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ14
|
||||
{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ14
|
||||
{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ14
|
||||
{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ14
|
||||
{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ15
|
||||
{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ15
|
||||
{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ15
|
||||
{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ15
|
||||
{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ15
|
||||
{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ16
|
||||
{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ16
|
||||
{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ16
|
||||
{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ16
|
||||
{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ16
|
||||
{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ17
|
||||
{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ17
|
||||
{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ17
|
||||
{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ17
|
||||
{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ17
|
||||
{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ18
|
||||
{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ18
|
||||
{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ18
|
||||
{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ18
|
||||
{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ18
|
||||
{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ19
|
||||
{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ19
|
||||
{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ19
|
||||
{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ19
|
||||
{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ19
|
||||
{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ20
|
||||
{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ20
|
||||
{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ20
|
||||
{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ20
|
||||
{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ20
|
||||
{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ21
|
||||
{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ21
|
||||
{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ21
|
||||
{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ21
|
||||
{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ21
|
||||
{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ22
|
||||
{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ22
|
||||
{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ22
|
||||
{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ22
|
||||
{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ22
|
||||
{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ23
|
||||
{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ23
|
||||
{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ23
|
||||
{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ23
|
||||
{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ23
|
||||
{0x73, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_Mixer1
|
||||
{0x74, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_2_Mixer2
|
||||
{0x75, 0x00, 0x80, 0x00, 0x00}, //##Channel_2_Prescale
|
||||
{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_Postscale
|
||||
{0x77, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x78, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x79, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7A, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7B, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7C, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7D, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC2_Power_Meter
|
||||
{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC4_Power_Meter
|
||||
{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC6_Power_Meter
|
||||
{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC8_Power_Meter
|
||||
{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN1
|
||||
{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN2
|
||||
{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN3
|
||||
{0x85, 0x00, 0x02, 0x00, 0x00}, //##DPEQ_Energy_Coefficient
|
||||
{0x86, 0x0D, 0x2D, 0x26, 0x00}, //##DPEQ_UP_TH
|
||||
{0x87, 0x0B, 0x83, 0xF1, 0x10}, //##DPEQ_Low_TH
|
||||
{0x88, 0x00, 0x26, 0x87, 0xF0}, //##DBE_1_div_(Upper-Lower)
|
||||
{0x89, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8A, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8B, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8C, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8D, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8E, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8F, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x90, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x91, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x92, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x93, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x94, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_RCH_GAIN
|
||||
{0x9A, 0x00, 0x5A, 0x9D, 0xF0}, //##AGC_Attach_threshold
|
||||
{0x9B, 0x00, 0x47, 0xFA, 0xD0}, //##AGC_Release_threshold
|
||||
{0x9C, 0x00, 0x00, 0x08, 0x64}, //##AGC_AR_RR
|
||||
{0x9D, 0x00, 0x00, 0x08, 0x64}, //##AGC_AT_RT
|
||||
{0x9E, 0x00, 0x10, 0x00, 0x00}, //##AGC ALPHA
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,511 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#if DEBUG_0
|
||||
static unsigned char eq_mode_2_reg_tab[AD82120B_REGISTER_COUNT][2] = {
|
||||
{0x00, 0x00}, //##State_Control_1
|
||||
{0x01, 0x82}, //##State_Control_2
|
||||
{0x02, 0x00}, //##State_Control_3
|
||||
{0x03, 0x40}, //##Master_volume_control
|
||||
{0x04, 0x18}, //##Channel_1_volume_control
|
||||
{0x05, 0x18}, //##Channel_2_volume_control
|
||||
{0x06, 0x18}, //##Channel_3_volume_control
|
||||
{0x07, 0x18}, //##Channel_4_volume_control
|
||||
{0x08, 0x18}, //##Channel_5_volume_control
|
||||
{0x09, 0x18}, //##Channel_6_volume_control
|
||||
{0x0A, 0x40}, //##DTC_Setting
|
||||
{0x0B, 0x00}, //##Reserve
|
||||
{0x0C, 0x90}, //##State_Control_4
|
||||
{0x0D, 0x80}, //##Channel_1_configuration_registers
|
||||
{0x0E, 0x80}, //##Channel_2_configuration_registers
|
||||
{0x0F, 0x80}, //##Channel_3_configuration_registers
|
||||
{0x10, 0x80}, //##Channel_4_configuration_registers
|
||||
{0x11, 0x80}, //##Channel_5_configuration_registers
|
||||
{0x12, 0x80}, //##Channel_6_configuration_registers
|
||||
{0x13, 0x80}, //##Channel_7_configuration_registers
|
||||
{0x14, 0x80}, //##Channel_8_configuration_registers
|
||||
{0x15, 0x00}, //##Reserve
|
||||
{0x16, 0x00}, //##Reserve
|
||||
{0x17, 0x00}, //##Reserve
|
||||
{0x18, 0x00}, //##Reserve
|
||||
{0x19, 0x80}, //##Reserve
|
||||
{0x1A, 0x28}, //##State_Control_5
|
||||
{0x1B, 0x80}, //##State_Control_6
|
||||
{0x1C, 0x20}, //##State_Control_7
|
||||
{0x1D, 0x00}, //##Coefficient_RAM_Base_Address
|
||||
{0x1E, 0x00}, //##First_4-bits_of_coefficients_A1
|
||||
{0x1F, 0x00}, //##Second_8-bits_of_coefficients_A1
|
||||
{0x20, 0x00}, //##Third_8-bits_of_coefficients_A1
|
||||
{0x21, 0x00}, //##Fourth-bits_of_coefficients_A1
|
||||
{0x22, 0x00}, //##First_4-bits_of_coefficients_A2
|
||||
{0x23, 0x00}, //##Second_8-bits_of_coefficients_A2
|
||||
{0x24, 0x00}, //##Third_8-bits_of_coefficients_A2
|
||||
{0x25, 0x00}, //##Fourth_8-bits_of_coefficients_A2
|
||||
{0x26, 0x00}, //##First_4-bits_of_coefficients_B1
|
||||
{0x27, 0x00}, //##Second_8-bits_of_coefficients_B1
|
||||
{0x28, 0x00}, //##Third_8-bits_of_coefficients_B1
|
||||
{0x29, 0x00}, //##Fourth_8-bits_of_coefficients_B1
|
||||
{0x2A, 0x00}, //##First_4-bits_of_coefficients_B2
|
||||
{0x2B, 0x00}, //##Second_8-bits_of_coefficients_B2
|
||||
{0x2C, 0x00}, //##Third_8-bits_of_coefficients_B2
|
||||
{0x2D, 0x00}, //##Fourth-bits_of_coefficients_B2
|
||||
{0x2E, 0x00}, //##First_4-bits_of_coefficients_A0
|
||||
{0x2F, 0x80}, //##Second_8-bits_of_coefficients_A0
|
||||
{0x30, 0x00}, //##Third_8-bits_of_coefficients_A0
|
||||
{0x31, 0x00}, //##Fourth_8-bits_of_coefficients_A0
|
||||
{0x32, 0x00}, //##Coefficient_RAM_R/W_control
|
||||
{0x33, 0x02}, //##State_Control_8
|
||||
{0x34, 0x00}, //##Reserve
|
||||
{0x35, 0x00}, //##Volume_Fine_tune
|
||||
{0x36, 0x00}, //##Volume_Fine_tune
|
||||
{0x37, 0xA0}, //##Device_ID_register
|
||||
{0x38, 0x00}, //##Level_Meter_Clear
|
||||
{0x39, 0x00}, //##Power_Meter_Clear
|
||||
{0x3A, 0x00}, //##First_8bits_of_C1_Level_Meter
|
||||
{0x3B, 0x00}, //##Second_8bits_of_C1_Level_Meter
|
||||
{0x3C, 0x00}, //##Third_8bits_of_C1_Level_Meter
|
||||
{0x3D, 0x00}, //##Fourth_8bits_of_C1_Level_Meter
|
||||
{0x3E, 0x00}, //##First_8bits_of_C2_Level_Meter
|
||||
{0x3F, 0x00}, //##Second_8bits_of_C2_Level_Meter
|
||||
{0x40, 0x00}, //##Third_8bits_of_C2_Level_Meter
|
||||
{0x41, 0x00}, //##Fourth_8bits_of_C2_Level_Meter
|
||||
{0x42, 0x00}, //##CHK_stat
|
||||
{0x43, 0x00}, //##First_4_bits_of_BEQ_CHK_val
|
||||
{0x44, 0x00}, //##Second_8_bits_of_BEQ_CHK_val
|
||||
{0x45, 0x00}, //##Third_4_bits_of_BEQ_CHK_val
|
||||
{0x46, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_val
|
||||
{0x47, 0x00}, //##First_4_bits_of_BEQ_CHK_result
|
||||
{0x48, 0x00}, //##Second_4_bits_of_BEQ_CHK_result
|
||||
{0x49, 0x00}, //##Third_4_bits_of_BEQ_CHK_result
|
||||
{0x4A, 0x00}, //##Bottom_4_bits_of_BEQ_CHK_result
|
||||
{0x4B, 0x10}, //##digital_DC_control
|
||||
{0x4C, 0x20}, //##digital_DC_judge_threshold
|
||||
{0x4D, 0xFF}, //##ERROR_register
|
||||
{0x4E, 0xFF}, //##ERROR_latch_register
|
||||
{0x4F, 0x00}, //##ERROR_clear_register
|
||||
{0x50, 0x01}, //##ERROR_register_2
|
||||
{0x51, 0x01}, //##ERROR_latch_register_2
|
||||
{0x52, 0x00}, //##ERROR_clear_register_2
|
||||
{0x53, 0x00}, //##Reserve
|
||||
{0x54, 0x00}, //##Reserve
|
||||
{0x55, 0x20}, //##clock_FS_detection
|
||||
{0x56, 0x10}, //##CLK_DET
|
||||
{0x57, 0x00}, //##TDM_word_width_selection
|
||||
{0x58, 0x00}, //##TDM_offset
|
||||
{0x59, 0x06}, //##I2S_Data_output_selection_register
|
||||
{0x5A, 0x08}, //##PWM_frequency_selection
|
||||
{0x5B, 0x00}, //##Mono_Key_High_Byte
|
||||
{0x5C, 0x00}, //##Mono_Key_Low_Byte
|
||||
{0x5D, 0x07}, //##Hi-res_Item
|
||||
{0x5E, 0x00}, //##analog_gain
|
||||
{0x5F, 0x00}, //##AGC_Control
|
||||
{0x60, 0x00}, //##Channel1_EQ_bypass_1
|
||||
{0x61, 0x00}, //##Channel1_EQ_bypass_2
|
||||
{0x62, 0x00}, //##Channel1_EQ_bypass_3
|
||||
{0x63, 0x00}, //##Channel2_EQ_bypass_1
|
||||
{0x64, 0x00}, //##Channel2_EQ_bypass_2
|
||||
{0x65, 0x00}, //##Channel2_EQ_bypass_3
|
||||
{0x66, 0x00}, //##ATTACK_HOLD_SET
|
||||
{0x67, 0x00}, //##Reserve
|
||||
{0x68, 0x00}, //##Reserve
|
||||
{0x69, 0x00}, //##Reserve
|
||||
{0x6A, 0x00}, //##Reserve
|
||||
{0x6B, 0x00}, //##Reserve
|
||||
{0x6C, 0x02}, //##FS_and_PMF_read_out
|
||||
{0x6D, 0x03}, //##OC_Selection
|
||||
{0x6E, 0x00}, //##digital_DC_control_testmode
|
||||
{0x6F, 0x32}, //##test_mode_register0
|
||||
{0x70, 0x07}, //##noise_gate_analog_gain
|
||||
{0x71, 0x41}, //##Testmode_register1
|
||||
{0x72, 0x38}, //##Testmode_register2
|
||||
{0x73, 0x18}, //##dither_signal_setting
|
||||
{0x74, 0x0D}, //##Error_Delay
|
||||
{0x75, 0x05}, //##First_4bits_of_MBIST_User_Program_Even
|
||||
{0x76, 0x55}, //##Second_8bits_of_MBIST_User_Program_Even
|
||||
{0x77, 0x55}, //##Third_8bits_of_MBIST_User_Program_Even
|
||||
{0x78, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Even
|
||||
{0x79, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Even
|
||||
{0x7A, 0x05}, //##First_8bits_of_MBIST_User_Program_Odd
|
||||
{0x7B, 0x55}, //##Second_8bits_of_MBIST_User_Program_Odd
|
||||
{0x7C, 0x55}, //##Third_8bits_of_MBIST_User_Program_Odd
|
||||
{0x7D, 0x55}, //##Fourth_8bits_of_MBIST_User_Program_Odd
|
||||
{0x7E, 0x55}, //##Fifth_8bits_of_MBIST_User_Program_Odd
|
||||
{0x7F, 0x50}, //##IP_shutdown_register
|
||||
{0x80, 0x00}, //##Protection_Register_Set
|
||||
{0x81, 0x00}, //##MBIST_Status
|
||||
{0x82, 0x00}, //##PWM_output_control
|
||||
{0x83, 0x00}, //##Test_Mode_Control
|
||||
{0x84, 0x00}, //##RAM1_test_register_address
|
||||
{0x85, 0x00}, //##First_4bits_of_RAM1_data
|
||||
{0x86, 0x00}, //##Second_8bits_of_RAM1_Data
|
||||
{0x87, 0x00}, //##Third_8bits_of_RAM1_data
|
||||
{0x88, 0x00}, //##Fourth_8bits_of_RAM1_Data
|
||||
{0x89, 0x00}, //##Fifth_8bits_of_RAM1_Data
|
||||
{0x8A, 0x00}, //##RAM1_test_r/w_control
|
||||
{0x8B, 0x00}, //##RAM2_test_register_address
|
||||
{0x8C, 0x00}, //##First_4bits_of_RAM2_data
|
||||
{0x8D, 0x00}, //##Second_8bits_of_RAM2_Data
|
||||
{0x8E, 0x00}, //##Third_8bits_of_RAM2_data
|
||||
{0x8F, 0x00}, //##Fourth_8bits_of_RAM2_Data
|
||||
{0x90, 0x00}, //##Fifth_8bits_of_RAM2_Data
|
||||
{0x91, 0x00}, //##RAM2_test_r/w_control
|
||||
{0x92, 0x00}, //##BURN_EN1
|
||||
{0x93, 0x00}, //##BURN_EN2
|
||||
{0x94, 0x00}, //##OSC_TRIM_CTRL
|
||||
{0x95, 0x80}, //##PLL_CTRL
|
||||
{0x96, 0x11}, //##PLL_CTRL2
|
||||
{0x97, 0x06}, //##CLKDET_read_out1
|
||||
{0x98, 0x11}, //##CLKDET_read_out2
|
||||
{0x99, 0x02}, //##CLKDET_read_out3
|
||||
{0x9A, 0x56}, //##CLKDET_read_out4
|
||||
{0x9B, 0x90}, //##CLKDET_read_out5
|
||||
{0x9C, 0x3F}, //##CLKDET_read_out6
|
||||
{0x9D, 0x00}, //##CLKDET_read_out7
|
||||
{0x9E, 0x02}, //##CLKDET_read_out8
|
||||
{0x9F, 0x02}, //##RECOUNT_CTRL
|
||||
{0xA0, 0xE4}, //##RECOUNT_STABLE_CTRL
|
||||
{0xA1, 0x04}, //##Auto_clock_detect_FS96k_window
|
||||
{0xA2, 0x04}, //##Auto_clock_detect_FS48k_window
|
||||
{0xA3, 0x04}, //##Auto_clock_detect_FS16k_window
|
||||
{0xA4, 0x04}, //##Auto_clock_detect_FS8k_window
|
||||
{0xA5, 0x80}, //##SYNC_LR
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef AD82120B_CHANGE_EQ_MODE_EN
|
||||
//###################RAM1_Table {RAM1 Address, Top Byte Of RAM1 Data ,
|
||||
//Middle Byte Of RAM1 Data , Botton Byte Of RAM1 Data }####################
|
||||
static unsigned char eq_mode_2_ram1_tab[][5] = {
|
||||
{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ1
|
||||
{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ1
|
||||
{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ1
|
||||
{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ1
|
||||
{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ1
|
||||
{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ2
|
||||
{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ2
|
||||
{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ2
|
||||
{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ2
|
||||
{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ2
|
||||
{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ3
|
||||
{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ3
|
||||
{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ3
|
||||
{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ3
|
||||
{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ3
|
||||
{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ4
|
||||
{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ4
|
||||
{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ4
|
||||
{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ4
|
||||
{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ4
|
||||
{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ5
|
||||
{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ5
|
||||
{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ5
|
||||
{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ5
|
||||
{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ5
|
||||
{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ6
|
||||
{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ6
|
||||
{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ6
|
||||
{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ6
|
||||
{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ6
|
||||
{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ7
|
||||
{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ7
|
||||
{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ7
|
||||
{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ7
|
||||
{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ7
|
||||
{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ8
|
||||
{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ8
|
||||
{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ8
|
||||
{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ8
|
||||
{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ8
|
||||
{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ9
|
||||
{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ9
|
||||
{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ9
|
||||
{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ9
|
||||
{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ9
|
||||
{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ10
|
||||
{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ10
|
||||
{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ10
|
||||
{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ10
|
||||
{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ10
|
||||
{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ11
|
||||
{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ11
|
||||
{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ11
|
||||
{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ11
|
||||
{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ11
|
||||
{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ12
|
||||
{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ12
|
||||
{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ12
|
||||
{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ12
|
||||
{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ12
|
||||
{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ13
|
||||
{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ13
|
||||
{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ13
|
||||
{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ13
|
||||
{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ13
|
||||
{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ14
|
||||
{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ14
|
||||
{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ14
|
||||
{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ14
|
||||
{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ14
|
||||
{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ15
|
||||
{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ15
|
||||
{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ15
|
||||
{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ15
|
||||
{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ15
|
||||
{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ16
|
||||
{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ16
|
||||
{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ16
|
||||
{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ16
|
||||
{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ16
|
||||
{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ17
|
||||
{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ17
|
||||
{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ17
|
||||
{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ17
|
||||
{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ17
|
||||
{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ18
|
||||
{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ18
|
||||
{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ18
|
||||
{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ18
|
||||
{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ18
|
||||
{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ19
|
||||
{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ19
|
||||
{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ19
|
||||
{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ19
|
||||
{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ19
|
||||
{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ20
|
||||
{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ20
|
||||
{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ20
|
||||
{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ20
|
||||
{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ20
|
||||
{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ21
|
||||
{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ21
|
||||
{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ21
|
||||
{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ21
|
||||
{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ21
|
||||
{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ22
|
||||
{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ22
|
||||
{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ22
|
||||
{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ22
|
||||
{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ22
|
||||
{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A1_EQ23
|
||||
{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_A2_EQ23
|
||||
{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B1_EQ23
|
||||
{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_B2_EQ23
|
||||
{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_A0_EQ23
|
||||
{0x73, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_1_Mixer1
|
||||
{0x74, 0x00, 0x00, 0x00, 0x00}, //##Channel_1_Mixer2
|
||||
{0x75, 0x00, 0x7E, 0x88, 0xE0}, //##Channel_1_Prescale
|
||||
{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_Postscale
|
||||
{0x77, 0x02, 0x00, 0x00, 0x00}, //##CH1.2_Power_Clipping
|
||||
{0x78, 0x00, 0x00, 0x01, 0xA0}, //####Noise_Gate_Attack_Level
|
||||
{0x79, 0x00, 0x00, 0x05, 0x30}, //##Noise_Gate_Release_Level
|
||||
{0x7A, 0x00, 0x01, 0x00, 0x00}, //##DRC1_Energy_Coefficient
|
||||
{0x7B, 0x00, 0x01, 0x00, 0x00}, //##DRC2_Energy_Coefficient
|
||||
{0x7C, 0x00, 0x01, 0x00, 0x00}, //##DRC3_Energy_Coefficient
|
||||
{0x7D, 0x00, 0x01, 0x00, 0x00}, //##DRC4_Energy_Coefficient
|
||||
{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC1_Power_Meter
|
||||
{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC3_Power_Meter
|
||||
{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC5_Power_Meter
|
||||
{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC7_Power_Meter
|
||||
{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN1
|
||||
{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN2
|
||||
{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_1_DRC_GAIN3
|
||||
{0x85, 0x0E, 0x01, 0xC0, 0x70}, //##DRC1_FF_threshold
|
||||
{0x86, 0x02, 0x00, 0x00, 0x00}, //##DRC1_FF_slope
|
||||
{0x87, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_aa
|
||||
{0x88, 0x00, 0x00, 0x40, 0x00}, //##DRC1_FF_da
|
||||
{0x89, 0x0E, 0x01, 0xC0, 0x70}, //##DRC2_FF_threshold
|
||||
{0x8A, 0x02, 0x00, 0x00, 0x00}, //##DRC2_FF_slope
|
||||
{0x8B, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_aa
|
||||
{0x8C, 0x00, 0x00, 0x40, 0x00}, //##DRC2_FF_da
|
||||
{0x8D, 0x0E, 0x01, 0xC0, 0x70}, //##DRC3_FF_threshold
|
||||
{0x8E, 0x02, 0x00, 0x00, 0x00}, //##DRC3_FF_slope
|
||||
{0x8F, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_aa
|
||||
{0x90, 0x00, 0x00, 0x40, 0x00}, //##DRC3_FF_da
|
||||
{0x91, 0x0E, 0x01, 0xC0, 0x70}, //##DRC4_FF_threshold
|
||||
{0x92, 0x02, 0x00, 0x00, 0x00}, //##DRC4_FF_slope
|
||||
{0x93, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_aa
|
||||
{0x94, 0x00, 0x00, 0x40, 0x00}, //##DRC4_FF_da
|
||||
{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_LCH_GAIN
|
||||
{0x9A, 0x02, 0x00, 0x00, 0x00}, //##SRS_Gain
|
||||
{0x9B, 0x01, 0xD7, 0xE6, 0xE0}, //##Compensate_A0
|
||||
{0x9C, 0x00, 0x2E, 0x77, 0x40}, //##Compensate_A1
|
||||
{0x9D, 0x0F, 0xF9, 0xA1, 0xE0}, //##Compensate_B1
|
||||
{0x9E, 0x01, 0x91, 0x2B, 0xE0}, //##QT_AT
|
||||
{0x9F, 0x01, 0x1B, 0x5A, 0xB9}, //##QT_RT
|
||||
{0xA0, 0x00, 0x5F, 0xCA, 0xCA}, //##QT_Region_T
|
||||
{0xA1, 0x00, 0x00, 0x00, 0x00}, //##QT_Region_B
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SND_SOC_AD82120B_2CHANNEL
|
||||
//###################RAM2_Table {RAM2 Address, Top Byte Of RAM2 Data ,
|
||||
//Middle Byte Of RAM2 Data , Botton Byte Of RAM2 Data }####################
|
||||
static unsigned char eq_mode_2_ram2_tab[][5] = {
|
||||
{0x00, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ1
|
||||
{0x01, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ1
|
||||
{0x02, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ1
|
||||
{0x03, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ1
|
||||
{0x04, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ1
|
||||
{0x05, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ2
|
||||
{0x06, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ2
|
||||
{0x07, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ2
|
||||
{0x08, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ2
|
||||
{0x09, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ2
|
||||
{0x0A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ3
|
||||
{0x0B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ3
|
||||
{0x0C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ3
|
||||
{0x0D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ3
|
||||
{0x0E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ3
|
||||
{0x0F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ4
|
||||
{0x10, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ4
|
||||
{0x11, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ4
|
||||
{0x12, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ4
|
||||
{0x13, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ4
|
||||
{0x14, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ5
|
||||
{0x15, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ5
|
||||
{0x16, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ5
|
||||
{0x17, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ5
|
||||
{0x18, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ5
|
||||
{0x19, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ6
|
||||
{0x1A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ6
|
||||
{0x1B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ6
|
||||
{0x1C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ6
|
||||
{0x1D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ6
|
||||
{0x1E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ7
|
||||
{0x1F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ7
|
||||
{0x20, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ7
|
||||
{0x21, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ7
|
||||
{0x22, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ7
|
||||
{0x23, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ8
|
||||
{0x24, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ8
|
||||
{0x25, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ8
|
||||
{0x26, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ8
|
||||
{0x27, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ8
|
||||
{0x28, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ9
|
||||
{0x29, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ9
|
||||
{0x2A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ9
|
||||
{0x2B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ9
|
||||
{0x2C, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ9
|
||||
{0x2D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ10
|
||||
{0x2E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ10
|
||||
{0x2F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ10
|
||||
{0x30, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ10
|
||||
{0x31, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ10
|
||||
{0x32, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ11
|
||||
{0x33, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ11
|
||||
{0x34, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ11
|
||||
{0x35, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ11
|
||||
{0x36, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ11
|
||||
{0x37, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ12
|
||||
{0x38, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ12
|
||||
{0x39, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ12
|
||||
{0x3A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ12
|
||||
{0x3B, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ12
|
||||
{0x3C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ13
|
||||
{0x3D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ13
|
||||
{0x3E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ13
|
||||
{0x3F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ13
|
||||
{0x40, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ13
|
||||
{0x41, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ14
|
||||
{0x42, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ14
|
||||
{0x43, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ14
|
||||
{0x44, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ14
|
||||
{0x45, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ14
|
||||
{0x46, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ15
|
||||
{0x47, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ15
|
||||
{0x48, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ15
|
||||
{0x49, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ15
|
||||
{0x4A, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ15
|
||||
{0x4B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ16
|
||||
{0x4C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ16
|
||||
{0x4D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ16
|
||||
{0x4E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ16
|
||||
{0x4F, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ16
|
||||
{0x50, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ17
|
||||
{0x51, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ17
|
||||
{0x52, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ17
|
||||
{0x53, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ17
|
||||
{0x54, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ17
|
||||
{0x55, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ18
|
||||
{0x56, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ18
|
||||
{0x57, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ18
|
||||
{0x58, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ18
|
||||
{0x59, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ18
|
||||
{0x5A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ19
|
||||
{0x5B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ19
|
||||
{0x5C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ19
|
||||
{0x5D, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ19
|
||||
{0x5E, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ19
|
||||
{0x5F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ20
|
||||
{0x60, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ20
|
||||
{0x61, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ20
|
||||
{0x62, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ20
|
||||
{0x63, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ20
|
||||
{0x64, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ21
|
||||
{0x65, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ21
|
||||
{0x66, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ21
|
||||
{0x67, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ21
|
||||
{0x68, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ21
|
||||
{0x69, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ22
|
||||
{0x6A, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ22
|
||||
{0x6B, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ22
|
||||
{0x6C, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ22
|
||||
{0x6D, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ22
|
||||
{0x6E, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A1_EQ23
|
||||
{0x6F, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_A2_EQ23
|
||||
{0x70, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B1_EQ23
|
||||
{0x71, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_B2_EQ23
|
||||
{0x72, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_A0_EQ23
|
||||
{0x73, 0x00, 0x00, 0x00, 0x00}, //##Channel_2_Mixer1
|
||||
{0x74, 0x07, 0xFF, 0xFF, 0xFF}, //##Channel_2_Mixer2
|
||||
{0x75, 0x00, 0x80, 0x00, 0x00}, //##Channel_2_Prescale
|
||||
{0x76, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_Postscale
|
||||
{0x77, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x78, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x79, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7A, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7B, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7C, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7D, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x7E, 0x00, 0x00, 0x00, 0x00}, //##DRC2_Power_Meter
|
||||
{0x7F, 0x00, 0x00, 0x00, 0x00}, //##DRC4_Power_Meter
|
||||
{0x80, 0x00, 0x00, 0x00, 0x00}, //##DRC6_Power_Meter
|
||||
{0x81, 0x00, 0x00, 0x00, 0x00}, //##DRC8_Power_Meter
|
||||
{0x82, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN1
|
||||
{0x83, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN2
|
||||
{0x84, 0x02, 0x00, 0x00, 0x00}, //##Channel_2_DRC_GAIN3
|
||||
{0x85, 0x00, 0x02, 0x00, 0x00}, //##DPEQ_Energy_Coefficient
|
||||
{0x86, 0x0D, 0x2D, 0x26, 0x00}, //##DPEQ_UP_TH
|
||||
{0x87, 0x0B, 0x83, 0xF1, 0x10}, //##DPEQ_Low_TH
|
||||
{0x88, 0x00, 0x26, 0x87, 0xF0}, //##DBE_1_div_(Upper-Lower)
|
||||
{0x89, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8A, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8B, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8C, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8D, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8E, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x8F, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x90, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x91, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x92, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x93, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x94, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x95, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x96, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x97, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x98, 0x00, 0x00, 0x00, 0x00}, //##Reserve
|
||||
{0x99, 0x00, 0x80, 0x00, 0x00}, //##I2SO_RCH_GAIN
|
||||
{0x9A, 0x00, 0x5A, 0x9D, 0xF0}, //##AGC_Attach_threshold
|
||||
{0x9B, 0x00, 0x47, 0xFA, 0xD0}, //##AGC_Release_threshold
|
||||
{0x9C, 0x00, 0x00, 0x08, 0x64}, //##AGC_AR_RR
|
||||
{0x9D, 0x00, 0x00, 0x08, 0x64}, //##AGC_AT_RT
|
||||
{0x9E, 0x00, 0x10, 0x00, 0x00}, //##AGC ALPHA
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user