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https://github.com/hardkernel/kernel_common_drivers.git
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vpu_security: miss config vd1 slice3 secure [1/1]
PD#SWPL-159826 Problem: miss config vd1 slice3 secure, the reg used for oled eco Solution: skip config vd1 slice3 secure Verify: t3x Change-Id: Idb46ff3690b90f29d47f13fb270f38f14636a235 Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
This commit is contained in:
Pengcheng Chen
committed by
gerrit autosubmit
gerrit autosubmit
parent
41b8a3ba39
commit
76bd00f805
@@ -312,119 +312,122 @@ u32 set_vpu_module_security(struct vpu_secure_ins *ins,
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struct vpu_sec_bit_s change;
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version = vpu_secure_version();
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if (is_vpu_secure_support()) {
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switch (module) {
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case OSD_MODULE:
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if ((secure_src & OSD1_INPUT_SECURE) ||
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(secure_src & OSD2_INPUT_SECURE) ||
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(secure_src & OSD3_INPUT_SECURE) ||
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(secure_src & OSD4_INPUT_SECURE) ||
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(secure_src & MALI_AFBCD_SECURE)) {
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/* for T7 revA */
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if (is_meson_t7_cpu() && is_meson_rev_a() &&
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(secure_src & (OSD1_INPUT_SECURE |
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OSD2_INPUT_SECURE)))
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secure_src |= OSD4_INPUT_SECURE;
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if (!is_vpu_secure_support())
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return 0;
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switch (module) {
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case OSD_MODULE:
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if ((secure_src & OSD1_INPUT_SECURE) ||
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(secure_src & OSD2_INPUT_SECURE) ||
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(secure_src & OSD3_INPUT_SECURE) ||
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(secure_src & OSD4_INPUT_SECURE) ||
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(secure_src & MALI_AFBCD_SECURE)) {
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/* for T7 revA */
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if (is_meson_t7_cpu() && is_meson_rev_a() &&
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(secure_src & (OSD1_INPUT_SECURE |
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OSD2_INPUT_SECURE)))
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secure_src |= OSD4_INPUT_SECURE;
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/* OSD module secure */
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osd_secure[vpp_index] = secure_src;
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value = osd_secure[vpp_index] |
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video_secure[vpp_index];
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ins->secure_enable = 1;
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ins->secure_status = value;
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osd_secure_en[vpp_index] = 1;
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} else {
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/* OSD none secure */
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osd_secure[vpp_index] = secure_src;
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value = osd_secure[vpp_index] |
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video_secure[vpp_index];
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ins->secure_enable = 0;
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ins->secure_status = value;
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osd_secure_en[vpp_index] = 0;
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}
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break;
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case VIDEO_MODULE:
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if ((secure_src & VD2_FGRAIN_SECURE) ||
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(secure_src & VD1_FGRAIN_SECURE) ||
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(secure_src & DV_INPUT_SECURE) ||
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(secure_src & AFBCD_INPUT_SECURE) ||
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(secure_src & VD3_INPUT_SECURE) ||
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(secure_src & VD2_INPUT_SECURE) ||
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(secure_src & VD1_INPUT_SECURE)) {
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/* video module secure */
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video_secure[vpp_index] = secure_src;
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value = video_secure[vpp_index] |
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osd_secure[vpp_index];
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if (version == VPU_SEC_V4) {
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u32 temp;
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/* OSD module secure */
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osd_secure[vpp_index] = secure_src;
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value = osd_secure[vpp_index] |
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video_secure[vpp_index];
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ins->secure_enable = 1;
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ins->secure_status = value;
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osd_secure_en[vpp_index] = 1;
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} else {
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/* OSD none secure */
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osd_secure[vpp_index] = secure_src;
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value = osd_secure[vpp_index] |
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video_secure[vpp_index];
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ins->secure_enable = 0;
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ins->secure_status = value;
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osd_secure_en[vpp_index] = 0;
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}
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break;
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case VIDEO_MODULE:
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if ((secure_src & VD2_FGRAIN_SECURE) ||
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(secure_src & VD1_FGRAIN_SECURE) ||
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(secure_src & DV_INPUT_SECURE) ||
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(secure_src & AFBCD_INPUT_SECURE) ||
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(secure_src & VD3_INPUT_SECURE) ||
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(secure_src & VD2_INPUT_SECURE) ||
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(secure_src & VD1_INPUT_SECURE)) {
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/* video module secure */
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video_secure[vpp_index] = secure_src;
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value = video_secure[vpp_index] |
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osd_secure[vpp_index];
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if (version == VPU_SEC_V4) {
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u32 temp;
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if (value & VD1_INPUT_SECURE) {
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if (value & VD1_INPUT_SECURE) {
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if (is_meson_t3x_cpu())
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temp = VD1_SLICE1_SECURE;
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else
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temp = VD1_SLICE1_SECURE |
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VD1_SLICE2_SECURE |
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VD1_SLICE3_SECURE;
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value |= temp;
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}
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value |= temp;
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}
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ins->secure_enable = 1;
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ins->secure_status = value;
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video_secure_en[vpp_index] = 1;
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} else {
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/* video module secure */
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video_secure[vpp_index] = secure_src;
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value = video_secure[vpp_index] |
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osd_secure[vpp_index];
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ins->secure_enable = 0;
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ins->secure_status = value;
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video_secure_en[vpp_index] = 0;
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}
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break;
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case DI_MODULE:
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break;
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case VDIN_MODULE:
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break;
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default:
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break;
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ins->secure_enable = 1;
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ins->secure_status = value;
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video_secure_en[vpp_index] = 1;
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} else {
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/* video module secure */
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video_secure[vpp_index] = secure_src;
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value = video_secure[vpp_index] |
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osd_secure[vpp_index];
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ins->secure_enable = 0;
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ins->secure_status = value;
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video_secure_en[vpp_index] = 0;
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}
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break;
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case DI_MODULE:
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break;
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case VDIN_MODULE:
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break;
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default:
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break;
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}
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if (version < VPU_SEC_V4 || version == VPU_SEC_V5) {
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vpp_top_en = osd_secure_en[vpp_index] ||
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video_secure_en[vpp_index];
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if (vpp_index == 0) {
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if (vpp_top_en)
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value |= VPP_OUTPUT_SECURE;
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else
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value &= ~VPP_OUTPUT_SECURE;
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}
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if (vpp_index == 1) {
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if (vpp_top_en)
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value |= VPP1_OUTPUT_SECURE;
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else
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value &= ~VPP1_OUTPUT_SECURE;
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}
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if (vpp_index == 2) {
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if (vpp_top_en)
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value |= VPP2_OUTPUT_SECURE;
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else
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value &= ~VPP2_OUTPUT_SECURE;
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}
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if (version < VPU_SEC_V4 || version == VPU_SEC_V5) {
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vpp_top_en = osd_secure_en[vpp_index] ||
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video_secure_en[vpp_index];
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if (vpp_index == 0) {
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if (vpp_top_en)
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value |= VPP_OUTPUT_SECURE;
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else
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value &= ~VPP_OUTPUT_SECURE;
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}
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/* debug value setting */
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if (debug_value)
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value = debug_value;
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if (vpp_index == 1) {
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if (vpp_top_en)
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value |= VPP1_OUTPUT_SECURE;
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else
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value &= ~VPP1_OUTPUT_SECURE;
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}
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if (vpp_index == 2) {
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if (vpp_top_en)
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value |= VPP2_OUTPUT_SECURE;
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else
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value &= ~VPP2_OUTPUT_SECURE;
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}
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}
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/* debug value setting */
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if (debug_value)
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value = debug_value;
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if (module == OSD_MODULE ||
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module == VIDEO_MODULE ||
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module == DI_MODULE) {
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if (value_save[vpp_index] != value) {
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/* record changed bit and current val */
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change.bit_changed =
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value ^ value_save[vpp_index];
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change.current_val = value;
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secure_reg_update(ins, &change, vpp_index);
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secure_update = 1;
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}
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value_save[vpp_index] = value;
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if (module == OSD_MODULE ||
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module == VIDEO_MODULE ||
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module == DI_MODULE) {
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if (value_save[vpp_index] != value) {
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/* record changed bit and current val */
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change.bit_changed =
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value ^ value_save[vpp_index];
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change.current_val = value;
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secure_reg_update(ins, &change, vpp_index);
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secure_update = 1;
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}
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value_save[vpp_index] = value;
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}
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if (log_level >= 2)
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